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ISP1520BD Datasheet(PDF) 11 Page - NXP Semiconductors |
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ISP1520BD Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 51 page Philips Semiconductors ISP1520 Hi-Speed USB hub controller Product data Rev. 02 — 04 May 2004 11 of 51 9397 750 11689 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 8.7 Power-on reset The ISP1520 has an internal Power-On Reset (POR) circuit. The triggering voltage of the POR circuit is 2.03 V nominal. A POR is automatically generated when VCC goes below the trigger voltage for a duration longer than 1 µs. At t1: clock is running and available. Fig 3. Power-on reset timing. Stable external clock is to be available at A. Fig 4. External clock with respect to power-on reset. 004aaa388 t1 VCC 2.03 V 0 V ≤ 683 µs POR POR EXTERNAL CLOCK A 004aaa365 |
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