SDRAM 16Mb H-die(x16)

CMOS SDRAM

Rev. 1.5 August 2004

Revision History

Revision 0.0 (May, 2003)

- Target spec release.

Revision 0.1 (October, 2003)

- Modified tRDL from 1CLK to 2CLK.

Revision 0.2 (October, 2003)

- Deleted AC parameter notes 5.

Revision 0.3 (October, 2003)

- Modified tRDL & deleted speed 200MHz.

Revision 1.0 (November, 2003)

- Revision 1.0 spec. release.

Revision 1.1 (December, 2003)

- Corrected PKG dimension.

Revision 1.2 (January, 2004)

- Deleted -10(10ns) speed.

- Modified load cap 50pF -> 30pF.

- Modified DC current .

Revision 1.3 (January, 2004)

- Corrected typo

Revision 1.4 (May, 2004)

- Added Note 8. sentense of tRDL parameter.

Revision 1.5 (August, 2004)

- Modified CLK cycle time(tcc) parameter in AC Characteristics.

( If you want use of CL=2 not CL=3, the maximum operating frequency is 100MHz regardless of its speed bin.)