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MAX191BEWG Datasheet(PDF) 8 Page - Maxim Integrated Products |
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MAX191BEWG Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 24 page _______________Detailed Description The MAX191 uses successive approximation and input track/hold (T/H) circuitry to convert an analog input sig- nal to a 12-bit digital output. Flexible control logic pro- vides easy interface to microprocessors (µPs), so most applications require only the addition of passive com- ponents. No external hold capacitor is required for the T/H. Figure 3 shows the MAX191 in its simplest opera- tional configuration. Pseudo-Differential Input The sampling architecture of the ADC’s analog com- parator is illustrated in the Equivalent Input Circuit (Figure 4). A capacitor switching between the AIN+ and AIN- inputs acquires the signal at the ADC’s ana- log input. At the end of the conversion, the capacitor reconnects to AIN+ and charges to the input signal. An external input buffer is usually not needed for low- bandwidth input signals (<100Hz) because the ADC disconnects from the input during the conversion. In unbuffered applications, an input filter capacitor reduces conversion noise, but also may limit input bandwidth. When converting a single-ended input signal, AIN- should be connected to AGND. If a differential signal is connected, consider that the configuration is pseudo differential—only the signal side to the input channel is held by the T/H. The return side (AIN-) must remain sta- ble within ±0.5LSB (±0.1LSB for best results) with respect to AGND during a conversion. Accomplish this by connecting a 0.1µF capacitor from AIN- to AGND. Analog Input—Track/Hold The T/H enters its tracking mode when the ADC is des- elected (CS pin is held high and BUSY pin is high). Hold mode starts approximately 25ns after a conver- sion is initiated. The variation in this delay from one conversion to the next (aperture jitter) is about 50ps. Figures 6–10 detail the T/H and interface timing for the Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down 8 _______________________________________________________________________________________ DN 3k CL DGND +5V 3k DN CL DGND a. High-Z to VOH and VOL to VOH b. High-Z to VOL and VOH to VOL Figure 1. Load Circuits for Access Time DN 3k 10pF DGND +5V 3k DN 10pF DGND a. VOH to High-Z b. VOL to High-Z Figure 2. Load Circuits for Bus-Relinquish Time 1 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 PD AIN+ AIN- VREF REFADJ AGND BIP BUSY DO/DB D1/D9 DGND VSS 2 VDD CLK/SCLK PAR HBEN CS RD D7/DOUT D6/SCLKOUT D5/SSTRB D4 D3/D11 D2/D10 OPEN OUTPUT STATUS 4.7 µF 0.1 µF 0.1 µF 0V TO -5V +5V SERIAL/PARALLEL INTERFACE MODE µP CONTROL INPUTS MAX191 C1 NOTE: C1 120pF GENERATES 1MHz NOMINAL CLOCK. µP DATA BUS Figure 3. Operational Diagram |
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