SN65HVD252_13 datasheet(4/18 Pages) TI1

Part #	SN65HVD252

Description	DeviceNet CAN Transceivers

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Manufacturer	TI1 [Texas Instruments]

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SN65HVD252

SN65HVD253

SLLSE37 – JUNE 2010

www.ti.com

THERMAL INFORMATION

HVD252/53

THERMAL METRIC

UNITS

8 PINS SOIC

qJA

Junction-to-ambient thermal resistance(1)

124.5

qJC(top)

Junction-to-case(top) thermal resistance (2)

55.9

qJB

Junction-to-board thermal resistance (3)

50.2

°C/W

yJT

Junction-to-top characterization parameter (4)

4.9

yJB

Junction-to-board characterization parameter (5)

46

qJC(bottom)

Junction-to-case(bottom) thermal resistance (6)

n/a

VCC = 5 V, TJ = 27°C, RL = 60Ω,

RS at 0 V, Input to D a 500-kHz

189.1

mW

50% duty cycle square wave

PD

Device power dissipation

VCC = 5.25 V, TJ = 150°C, RL = 50Ω,

RS at 0 V, Input to D a 500-kHz

274.8

mW

50% duty cycle square wave

(1)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(2)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(4)

The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).

(5)

The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).

(6)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

DRIVER ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP(1)

MAX

UNIT

CANH

2.75

3.5

4.5

Bus output voltage

See Figure 1, TXD = 0 V, S = 0 V, AB = 0 V (HVD253),

VO(D)

V

(dominant)

RCM = open, CL = open, RL = 60 Ω

CANL

0.5

1.5

2.25

VO(R)

Bus output voltage (recessive)

TXD = 3 V, S = 0 V

No Load

2

2.5

3

V

See Figure 1, TXD = 0 V, S = 0 V, RCM = open,

1.5

2.4

3.4

CL = open, 45 Ω ≤ RL ≤ 60 Ω

Differential output voltage

VOD(D)

V

(dominant)

See Figure 1, TXD = 0 V, S = 0 V, RL = 60 Ω,

1.2

2.6

3.3

RCM = 330 Ω, CL = open, –5 V < VCM < 10 V

RL = 60 Ω

–12

12

Differential output voltage

See Figure 1, TXD = 3 V, S = 0 V,

VOD(R)

mV

(recessive)

RCM = open, CL = 100 pF

No load

–100

50

Output symmetry (dominant or

See Figure 1, S = 0 V, AB = 0 V (HVD253), RCM = open,

VSYM

–400

0

400

mV

recessive)

CL = open, RL = 60 Ω, VSYM = VCC – VCANH – VCANL

–5 V < VCANH < 10 V, CANL open

–350

2.5

Short-circuit steady-state output

IOS(ss)

mA

current

–5 V < VCANL < 10 V, CANH open

–2.5

350

(1)

All typical values are at 25°C with VCC = 5 V.

DRIVER SWITCHING CHARACTERISTICS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tpHR

Propagation delay time, high input to recessive output

50

70

tpLD

Propagation delay time, low input to dominant output

40

70

See Figure 1, S = 0 V, RL = 60 Ω,

ns

CL = 100 pF, RCM = open

tr

Differential output signal rise time, 10% to 90%

15

30

tf

Differential output signal fall time, 90% to 10%

17

30

RL = 60 Ω, CL = 15 pF,

ten

Enable time from silent mode to dominant

200

ns

CLD = 100 pF

4

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