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PC87392-VJG Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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PC87392-VJG Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 148 page Table of Contents (Continued) 6 www.national.com 2.7.2 GPIO Pin Function Lock .............................................................................................. 36 2.8 LPC INTERFACE ...................................................................................................................... 36 2.8.1 LPC Transactions Supported ...................................................................................... 36 2.8.2 CLKRUN Functionality ................................................................................................. 37 2.8.3 LPCPD Functionality ................................................................................................... 37 2.9 REGISTER TYPE ABBREVIATIONS ........................................................................................ 37 2.10 SUPERI/O CONFIGURATION REGISTERS ............................................................................. 37 2.10.1 SuperI/O ID Register (SID) .......................................................................................... 38 2.10.2 SuperI/O Configuration 1 Register (SIOCF1) .............................................................. 38 2.10.3 SuperI/O Configuration 2 Register (SIOCF2) .............................................................. 39 2.10.4 SuperI/O Configuration 3 Register (SIOCF3) .............................................................. 40 2.10.5 SuperI/O Configuration 4 Register (SIOCF4) .............................................................. 41 2.10.6 SuperI/O Configuration 5 Register (SIOCF5) .............................................................. 42 2.10.7 SuperI/O Configuration 6 Register (SIOCF6) .............................................................. 43 2.10.8 SuperI/O Revision ID Register (SRID) ........................................................................ 43 2.10.9 SuperI/O Configuration 8 Register (SIOCF8) .............................................................. 44 2.10.10 SuperI/O Configuration 9 Register (SIOCF9) .............................................................. 45 2.10.11 SuperI/O Configuration A Register (SIOCFA) ............................................................. 46 2.11 FLOPPY DISK CONTROLLER (FDC) CONFIGURATION ........................................................ 47 2.11.1 General Description ..................................................................................................... 47 2.11.2 Logical Device 0 (FDC) Configuration ......................................................................... 47 2.11.3 FDC Configuration Register ........................................................................................ 48 2.11.4 Drive ID Register .........................................................................................................49 2.12 PARALLEL PORT CONFIGURATION ...................................................................................... 50 2.12.1 General Description ..................................................................................................... 50 2.12.2 Logical Device 1 (PP) Configuration ............................................................................ 51 2.12.3 Parallel Port Configuration Register ............................................................................ 52 2.13 SERIAL PORT 2 CONFIGURATION ......................................................................................... 53 2.13.1 General Description ..................................................................................................... 53 2.13.2 Logical Device 2 (SP2) Configuration .......................................................................... 53 2.13.3 Serial Port 2 Configuration Register ............................................................................ 54 2.14 SERIAL PORT 1 CONFIGURATION ......................................................................................... 55 2.14.1 Logical Device 3 (SP1) Configuration .......................................................................... 55 2.14.2 Serial Port 1 Configuration Register ............................................................................ 55 2.15 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION .......................... 56 2.15.1 General Description ..................................................................................................... 56 2.15.2 Implementation ............................................................................................................56 2.15.3 Logical Device 7 (GPIO) Configuration ....................................................................... 57 2.15.4 GPIO Pin Select Register ............................................................................................ 58 2.15.5 GPIO Pin Configuration Register ................................................................................. 59 2.15.6 GPIO Event Routing Register ...................................................................................... 60 2.16 WATCHDOG TIMER (WDT) CONFIGURATION ...................................................................... 61 2.16.1 Logical Device 10 (WDT) Configuration ...................................................................... 61 2.16.2 WATCHDOG Timer Configuration Register ................................................................ 61 |
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