SA8028 datasheet(6/28 Pages) PHILIPS

Part #	SA8028

Description	2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers

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Manufacturer	PHILIPS [NXP Semiconductors]

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Philips Semiconductors

Product data

SA8028

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

2002 Feb 22

6

CHARACTERISTICS

VDDCP = VDD = VDDpre= +3.0 V, Tamb = +25°C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

VDD,

VDDpre

Digital supply voltage, prescaler supply voltage

VDD = VDDpre

2.7

–

3.6

V

VDDCP

Charge pump supply voltage

VDDCP ≥ VDD, VDDpre

2.7

–

3.6

V

IDDTotal

Synthesizer operational total supply current

fREF = 20 MHz

(with RF on, IF on)

–

7.6

–

mA

(with RF on, IF off)

–

6.4

–

mA

IDDsleep

Total supply current in power-down mode

logic levels 0 or VDD

–

0.1

1

µA

RF divider input

fRFin

RF VCO input frequency range

500

–

2500

MHz

VRFin

AC-coupled input signal level

Rin (external) = Rs = 50 Ω;

single-ended drive;

–15

–

0

dBm

g

max. limit is indicative

@ 500 to 2500 MHz

112

–

632

mVpp

ZRFin

Input impedance Re (Z)

fRFin = 2.4 GHz

–

300

–

Ω

CRFin

Typical pin input capacitance

fRFin = 2.4 GHz

–

1

–

pF

NRF

RF divider ratio ranges

Limited test coverage

33

–

509

FCOMPmax

Maximum phase comparator frequency

RF phase comparator

–

30

MHz

IF divider input

fIFin

Input frequency range

100

–

760

MHz

VIFin

AC-coupled input signal level

fIFin: 100 MHz to 500 MHz

R (external)

R

50

Ω;

–15

–

0

dBm

Rin (external) = RS = 50 Ω;

max. limit is indicative

112

–

632

mVpp

fIFin: 500 MHz to 760 MHz

R (external)

R

50

Ω;

–10

–

0

dBm

Rin (external) = RS = 50 Ω;

max. limit is indicative

200

–

632

mVpp

ZFin

Input impedance Re (Z)

fRFin = 500 MHz

–

3.9

–

k

Ω

CFin

Typical pin input capacitance

fRFin = 500 MHz

–

0.5

–

pF

NIF

IF division ratio

128

–

16383

Reference divider input

fREFin

Input frequency range from TCXO

5

–

30

MHz

VREFin

AC-coupled input signal level

single-ended drive;

max. limit is indicative

360

–

1300

mVPP

ZREFin

Input impedance Re (Z)

fREF = 20 MHz

–

10

–

k

Ω

CREFin

Typical pin input capacitance

fREF = 20 MHz

–

1

–

pF

RREF

Reference division ratio

SA = ”000”, IF loop

4

–

1023

Charge pump current setting resistor input

RSET

External resistor from pin to ground

6

7.5

15

k

Ω

VSET

Regulated voltage at pin

RSET = 7.5 kΩ

–

1.22

–

V

Charge pump outputs; RSET = 7.5 kΩ

ICP

Charge pump current ratio to ISET1

Current gain = IPH/ISET

–15

–

+15

%

IMATCH

Sink-to-source current matching

VPH = 1/2 VDDCP

–10

–

+10

%

IZOUT

Output current variation versus VPH2

VPH in compliance range

–10

–

+10

%

ILPH

Charge pump off leakage current

VPH = 1/2 VDDCP

–10

–

+10

nA

VPH

Charge pump voltage compliance

0.6

–

VDDCP–0.7 V

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SA8028 Datasheet(PDF) 6 Page - NXP Semiconductors

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