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DP8420A Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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DP8420A Datasheet(HTML) 5 Page - National Semiconductor (TI) |
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5 / 58 page  20 Signal Descriptions Pin Device (If not Input Description Name Applicable to All) Output 21 ADDRESS RW AND PROGRAMMING SIGNALS R0 – 10 DP8422A I ROW ADDRESS These inputs are used to specify the row address during an access to the DRAM They are also used to program the chip when ML is asserted (except R0 – 9 DP8420A21A I R10) C0 – 10 DP8422A I COLUMN ADDRESS These inputs are used to specify the column address during an access to the DRAM They are also used to program the chip when ML is asserted C0 – 9 DP8420A21A I (except C10) B0 B1 I BANK SELECT Depending on programming these inputs are used to select a group of RAS and CAS outputs to assert during an access They are also used to program the chip when ML is asserted ECAS0–3 I ENABLE CAS These inputs are used to enable a single or group of CAS outputs when asserted In combination with the B0 B1 and the programming bits these inputs select which CAS output or CAS outputs will assert during an access The ECAS signals can also be used to toggle a group of CAS outputs for pagenibble mode accesses They also can be used for byte write operations If ECAS0is negated during programming continuing to assert the ECAS0 while negating AREQ or AREQB during an access will cause the CAS outputs to be extended while the RAS outputs are negated (the ECASn inputs have no effect during scrubbing refreshes) WIN I WRITE ENABLE IN This input is used to signify a write operation to the DRAM If ECAS0 is asserted during programming the WE output will follow this input This input asserted will also cause CAS to delay to the next positive clock edge if address bit C9 is asserted during programming COLINC I COLUMN INCREMENT When the address latches are used and RFIP is negated this input functions as COLINC Asserting this signal causes the column address to (EXTNDRF) I be incremented by one When RFIP is asserted this signal is used to extend the refresh cycle by any number of periods of CLK until it is negated ML I MODE LOAD This input signal when low enables the internal programming register that stores the programming information 22 DRAM CONTROL SIGNALS Q0 – 10 DP8422A O DRAM ADDRESS These outputs are the multiplexed output of the R0 – 9 10 and C0 – 9 10 and form the DRAM address bus These outputs contain the refresh Q0 – 9 DP8421A O address whenever RFIP is asserted They contain high capacitive drivers with 20X Q0 – 8 DP8421A O series damping resistors RAS0–3 O ROW ADDRESS STROBES These outputs are asserted to latch the row address contained on the outputs Q0 – 8 9 10 into the DRAM When RFIP is asserted the RAS outputs are used to latch the refresh row address contained on the Q0 – 8 9 10 outputs in the DRAM These outputs contain high capacitive drivers with 20X series damping resistors CAS0–3 O COLUMN ADDRESS STROBES These outputs are asserted to latch the column address contained on the outputs Q0 – 8 9 10 into the DRAM These outputs have high capacitive drivers with 20X series damping resistors WE O WRITE ENABLE or REFRESH REQUEST This output asserted specifies a write operation to the DRAM When negated this output specifies a read operation to the (RFRQ)O DRAM When the DP8420A21A22A is programmed in address pipelining mode or when ECAS0 is negated during programming this output will function as RFRQ When asserted this pin specifies that 13 msor15 ms have passed If DISRFSH is negated the DP8420A21A22A will perform an internal refresh as soon as possible If DISRFRSH is asserted RFRQ can be used to externally request a refresh through the input RFSH This output has a high capacitive driver and a 20X series damping resistor 5 |
Similar Part No. - DP8420A |
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Similar Description - DP8420A |
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