SN54LVT18502

3.3-V ABT SCAN TEST DEVICE

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS669 – JULY 1996

1

POST OFFICE BOX 655303

Family of Testability Products

Widebus

™ Family

Mixed-Mode Signal Operation (5-V Input

Down to 2.7 V

Combines D-Type Latches and D-Type

Flip-Flops for Operation in Transparent,

Latched, or Clocked Mode

Need for External Pullup Resistors

1149.1-1990 (JTAG) Test Access Port and

Boundary-Scan Architecture

– IEEE Standard 1149.1-1990 Required

Instructions and Optional CLAMP and

HIGHZ

– Parallel-Signature Analysis at Inputs

– Pseudo-Random Pattern Generation

From Outputs

– Sample Inputs/Toggle Outputs

– Binary Count From Outputs

– Device Identification

– Even-Parity Opcodes

Packages Using 25-mil Center-to-Center

Spacings

1B4

1B5

1B6

GND

1B7

1B8

1B9

NC

2B1

2B2

2B3

2B4

GND

2B5

2B6

2B7

1A3

1A4

1A5

GND

1A6

1A7

1A8

1A9

NC

2A1

2A2

2A3

GND

2A4

2A5

2A6

HV PACKAGE

(TOP VIEW)

NC – No internal connection

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

28 29 30 31 32 33 34

87

6

5

4

93

1 68 67

2

35 36 37 38 39

66 65

27

64 63 62 61

40 41 42 43

Copyright

© 1996, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE, Widebus, and UBT are trademarks of Texas Instruments Incorporated.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.