Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

SN65LV1224BMDBREP Datasheet(PDF) 4 Page - Texas Instruments

Click here to check the latest version.
Part # SN65LV1224BMDBREP
Description  10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
Download  25 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN65LV1224BMDBREP Datasheet(HTML) 4 Page - Texas Instruments

  SN65LV1224BMDBREP Datasheet HTML 1Page - Texas Instruments SN65LV1224BMDBREP Datasheet HTML 2Page - Texas Instruments SN65LV1224BMDBREP Datasheet HTML 3Page - Texas Instruments SN65LV1224BMDBREP Datasheet HTML 4Page - Texas Instruments SN65LV1224BMDBREP Datasheet HTML 5Page - Texas Instruments SN65LV1224BMDBREP Datasheet HTML 6Page - Texas Instruments SN65LV1224BMDBREP Datasheet HTML 7Page - Texas Instruments SN65LV1224BMDBREP Datasheet HTML 8Page - Texas Instruments SN65LV1224BMDBREP Datasheet HTML 9Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 25 page
background image
www.ti.com
INITIALIZATION MODE
SYNCHRONIZATION MODE
SN65LV1023A-EP
SN65LV1224B-EP
SGLS358 – SEPTEMBER 2006
FUNCTIONAL DESCRIPTION (continued)
Initialization of both devices must occur before data transmission can commence. Initialization refers to
synchronization of the serializer and deserializer PLLs to local clocks.
When VCC is applied to the serializer and/or deserializer, the respective outputs enter the high-impedance state,
while on-chip power-on circuitry disables internal circuitry. When VCC reaches 2.45 V, the PLL in each device
begins locking to a local clock. For the serializer, the local clock is the transmit clock (TCLK) provided by an
external source. For the deserializer, a local clock must be applied to the REFCLK pin. The serializer outputs
remain in the high-impedance state, while the PLL locks to the TCLK.
The deserializer PLL must synchronize to the serializer in order to receive valid data. Synchronization can be
accomplished in one of two ways:
Rapid Synchronization: The serializer has the capability to send specific SYNC patterns consisting of six
ones and six zeros switching at the input clock rate. The transmission of SYNC patterns enables the
deserializer to lock to the serializer signal within a deterministic time frame. This transmission of SYNC
patterns is selected via the SYNC1 and SYNC2 inputs on the serializer. Upon receiving valid SYNC1 or
SYNC2 pulse (wider than 6 clock cycles), 1026 cycles of SYNC pattern are sent.
When the deserializer detects edge transitions at the LVDS input, it attempts to lock to the embedded clock
information. The deserializer LOCK output remains high while its PLL locks to the incoming data or SYNC
patterns present on the serial input. When the deserializer locks to the LVDS data, the LOCK output goes
low. When LOCK is low, the deserializer outputs represent incoming LVDS data. One approach is to tie the
deserializer LOCK output directly to SYNC1 or SYNC2.
Random-Lock Synchronization: The deserializer can attain lock to a data stream without requiring the
serializer to send special SYNC patterns. This allows the SN65LV1224B to operate in open-loop
applications. Equally important is the deserializer’s ability to support hot insertion into a running backplane.
In the open-loop or hot-insertion case, it is assumed the data stream is essentially random. Therefore,
because lock time varies due to data stream characteristics, the exact lock time cannot be predicted. The
primary constraint on the random lock time is the initial phase relation between the incoming data and the
REFCLK when the deserializer powers up.
The data contained in the data stream can also affect lock time. If a specific pattern is repetitive, the deserializer
could enter false lock—falsely recognizing the data pattern as the start/stop bits. This is referred to as repetitive
multitransition (RMT); see Figure 2 for RMT examples. This occurs when more than one low-high transition
takes place per clock cycle over multiple cycles. In the worst case, the deserializer could become locked to the
data pattern rather than the clock. Circuitry within the deserializer can detect that the possibility of false lock
exists. Upon detection, the circuitry prevents the LOCK output from becoming active until the potential false lock
pattern changes. Notice that the RMT pattern only affects the deserializer lock time, and once the deserializer is
in lock, the RMT pattern does not affect the deserializer state as long as the same data boundary happens each
cycle. The deserializer does not go into lock until it finds a unique four consecutive cycles of data boundary
(stop/start bits) at the same position.
The deserializer stays in lock until it cannot detect the same data boundary (stop/start bits) for four consecutive
cycles. Then the deserializer goes out of lock and hunts for the new data boundary (stop/start bits). In the event
of loss of synchronization, the LOCK pin output goes high and the outputs (including RCLK) enter a
high-impedance state. The user’s system should monitor the LOCK pin in order to detect a loss of
synchronization. Upon detection of loss of lock, sending sync patterns for resynchronization is desirable if
reestablishing lock within a specific time is critical. However, the deserializer can lock to random data as
previously noted.
4
Submit Documentation Feedback


Similar Part No. - SN65LV1224BMDBREP

ManufacturerPart #DatasheetDescription
logo
Texas Instruments
SN65LV1224BMDBREP TI1-SN65LV1224BMDBREP Datasheet
562Kb / 25P
[Old version datasheet]   10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
More results

Similar Description - SN65LV1224BMDBREP

ManufacturerPart #DatasheetDescription
logo
Texas Instruments
SN65LV1023A TI-SN65LV1023A Datasheet
314Kb / 22P
[Old version datasheet]   10-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SN65LV1023A TI1-SN65LV1023A_16 Datasheet
938Kb / 29P
[Old version datasheet]   10-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SN65LV1023A-EP TI1-SN65LV1023A-EP Datasheet
562Kb / 25P
[Old version datasheet]   10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SN65LV1023A TI-SN65LV1023A_07 Datasheet
717Kb / 29P
[Old version datasheet]   10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SN65LV1021 TI-SN65LV1021 Datasheet
266Kb / 19P
[Old version datasheet]   10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SN65LV1021 TI1-SN65LV1021_08 Datasheet
409Kb / 22P
[Old version datasheet]   10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SN65LV1023 TI-SN65LV1023 Datasheet
292Kb / 20P
[Old version datasheet]   30 MHZ TO 66MHZ 10:1 LVDS SERIALIZER/DESERIALIZER
logo
National Semiconductor ...
SCAN921023 NSC-SCAN921023 Datasheet
508Kb / 20P
   20-66 MHz 10 Bit Bus LVDS Serializer and Deserializer
logo
Texas Instruments
DS92LV1023E TI1-DS92LV1023E_14 Datasheet
963Kb / 21P
[Old version datasheet]   30-66 MHz 10 Bit Bus LVDS Serializer
logo
National Semiconductor ...
DS92LV1224 NSC-DS92LV1224 Datasheet
799Kb / 16P
   30-66 MHz 10 Bit Bus LVDS Deserializer
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com