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DESERIALIZER SWITCHING CHARACTERISTICS

SN65LV1023A

SN65LV1224A

SLLS570D – JUNE 2003 – REVISED JANUARY 2005

over recommended operating supply and temperature ranges (unless otherwise specified)

PARAMETER

TEST CONDITIONS

PIN/FREQ

MIN

TYP

MAX

UNIT

Receiver out

RCLK

15.15

100

ns

clockperiod

See Figure 12

CMOS/TTL

low-to-high transition

1.2

2.5

time

ns

See Figure 6

LOCK, RCLK

CMOS/TTL

high-to-low transition

1.1

2.5

time

10 MHz

Deserializer delay,

Room temperature,

ns

See Figure 13

3.3 V

66 MHz

RCLK 10 MHz

before RCLK

RCLK 66 MHz

See Figure 14

ns

10 MHz

RCLK

66 MHz

RCLK duty cycle

40%

50%

60%

High-to-high-

impedance state

6.5

8

ns

delay

Low-to-high-

impedance state

4.7

8

ns

See Figure 15

delay

High-impedance

5.3

8

ns

state-to-high delay

High-impedance-

4.7

8

ns

state-to-low delay

Deserializer PLL lock

10 MHz

time from

PWRDN(with

66 MHz

µs

SYNCPAT)

See Figure 16,

10 MHz

0.7

Deserializer PLL lock

time from SYNCPAT

66 MHz

0.2

High-impedance-state

to-high delay(power

LOCK

3

ns

up)

10 MHz

3680

Deserializer noise

ps

margin

66 MHz

540

(1)

The deserializer delay time for all frequencies does not exceed 2 serial bit times.

(2)

when the input (RI

±) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). In order to specify

(3)

10

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