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SN65LVDS93DGGR Datasheet(PDF) 11 Page - Texas Instruments |
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SN65LVDS93DGGR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 19 page SN74FB2032 8 D0–D7 8 D8–D15 SN65LVDS93 LVDS Interface 0 To 10 Meters (Media Dependent) TTL Interface W/Parity 16-Bit BTL Bus Interface CLK Backplane Bus 8 D0–D7 8 D8–D15 CLK Backplane Bus TTL Interface 16-Bit BTL Bus Interface XMIT Clock RCV Clock 9 Bit Latchable Transceiver/ With Parity Generator Parity Parity TTL Interface Parity Parity Parity Error TTL Interface W/Parity SN74FB2032 9 Bit Latchable Transceiver/ With Parity Generator SN74FB2032 SN74FB2032 9 Bit Latchable Transceiver/ With Parity Generator 9 Bit Latchable Transceiver/ With Parity Generator SN65LVDS94 low cost virtual backplane transceiver Bus Transceivers LVDS Serdes Transmitter LVDS Serdes Receiver Bus Transceivers TTL Inputs Up To 21 or 28 Bits LVDS Serial Links 4 or 5 Pairs TTL Outputs Up To 21 or 28 Bits Bus Transceivers LVDS Serdes Transmitter LVDS Serdes Receiver Bus Transceivers Backplane Bus Backplane Bus SN65LVDS93 www.ti.com ................................................................................................................................................................. SLLS302G – MAY 1998 – REVISED MAY 2009 Figure 11. 16-Bit Bus Extension With Parity Figure 12 represents LVDS serdes in an application as a virtual backplane transceiver (VBT). The concept of a VBT can be achieved by implementing individual LVDS serdes chipsets in both directions of subsystem serialized links. Depending on the application, the designer will face varying choices when implementing a VBT. In addition to the devices shown in Figure 12, functions such as parity and delay lines for control signals could be included. Using additional circuitry, half-duplex or full-duplex operation can be achieved by configuring the clock and control lines properly. The designer may choose to implement an independent clock oscillator at each end of the link and then use a PLL to synchronize LVDS serdes's parallel I/O to the backplane bus. Resynchronizing FIFOs may also be required. Figure 12. Virtual Backplane Transceiver Copyright © 1998–2009, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s) :SN65LVDS93 |
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