SN65LVDS311

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SLLSE31B – MAY 2010 – REVISED MARCH 2013

INPUT ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

PCLK, R[0:7], G[0:7], B[0:7], VS, HS, DE, PCLK, LS[1:0], TXEN, SWAP

High-level input current

–200

200

nA

Low-level input current

–200

200

Input capacitance

1.5

pF

(1)

All typical values are at 25°C and with 1.8 V supply unless otherwise noted.

SWITCHING CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

20%-to-80% differential

See Figure 7 and Figure 8

250

500

output signal rise time

ps

20%-to-80% differential

See Figure 7 and Figure 8

250

500

output signal fall time

Tested from PCLK input to

PLL bandwidth (3dB cutoff

MHz

CLK output, See Figure 5 (2)

frequency)

Propagation delay time,

1-channel mode

input to serial output (data

2-channel mode

s

latency Figure 9)

3-channel mode

Output CLK duty cycle

1-channel and 3-channel

0.45

0.50

0.55

mode

2-channel mode

0.49

0.53

0.58

TXEN Glitch suppression

3.8

10

μs

see Figure 12 and Figure 13

Enable time from power

Time from TXEN pulled high to CLK and Dx outputs

0.24

2

ms

down (

↑TXEN)

enabled and transmit valid data; see Figure 13

Disable time from active

TXEN is pulled low during transmit mode; time

0.5

11

mode (

↓TXEN)

measurement until output is disabled and PLL is Shutdown;

μs

see Figure 13

Enable time from Standby

0.23

2

(

↕PCLK)

PCLK starts switching to CLK and Dx outputs enabled and

ms

transmit valid data; see Figure 13

Disable time from Active

0.4

100

mode (PCLK stopping)

from PCLK input signal stops until CLK + Dx outputs are

μs

disabled and PLL is disabled; see Figure 13

(1)

All typical values are at 25°C and with 1.8 V supply unless otherwise noted.

(2)

The Maximum Limit is based on statistical analysis of the device performance over process, voltage, and temp ranges. This parameter

is functionality tested only on Automatic Test Equipment (ATE).

(3)

to-high transition that is suppressed.

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