REF

RLIM

IPx

REx

FGND

5 V

Shift Register

CP

D

Q

S

R

CP

D

Q

S

R

CP

D

Q

S

R

CP

D

Q

S

R

CP

D

Q

S

R

CP

D

Q

S

R

CP

D

Q

S

R

SOP

SIP

CLK

CE

LD

UVO

HOT

PIP 0

PIP 1

PIP 6

PIP 7

PAR

Logic

SN65HVS881

Figure 14. Equivalent Input Diagram

The conversion from parallel input- to serial output data is performed by an eight channel parallel-in serial-out

shift register. Parallel-in access is provided by the internal inputs, PIP0–PIP7 that are enabled by a low level at

the load input (LD). When clocked, the latched input data shift towards the serial output (SOP). The shift register

also provides a clock-enable function.

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while LD is held high and the clock

enable (CE) input is held low. Parallel loading is inhibited when /LD is held high. The parallel inputs to the

register are enabled while LD is low independently of the levels of the CLK, CE, or serial (SIP) inputs.

Figure 15. Shift Register Logic Structure

Copyright © 2009, Texas Instruments Incorporated

Submit Documentation Feedback

11

Product Folder Link(s): SN65HVS881