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DP8440VLJ-40 Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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DP8440VLJ-40 Datasheet(HTML) 10 Page - National Semiconductor (TI) |
10 / 46 page 40 Programming and Resetting 41 RESET After power up the DP844041 must be reset and pro- grammed before it can be used to access the DRAM Reset is accomplished by asserting the input RESET for at least 16 positive edges of CLK after VCC stabilizes After reset the part can be programmed 42 PROGRAMMING Programming is accomplished by presenting a valid pro- gramming selection on the row column bank selects and ECAS inputs and toggling the ML input from low to high When ML goes high the part is programmed After the first programming after a reset the part will enter a 60 ms initiali- zation period During this period the controller will refresh the memory so further DRAM warm up cycles are not nec- essary The user can program the part on the fly by pulsing ML low and high (provided that no refresh is in progress) while a valid programming selection is on the address bus The part will not enter the initialization period when it is only re-programmed TLF11718 – 4 FIGURE 5 Reset TLF11718 – 5 FIGURE 6 Programming 10 |
Similar Part No. - DP8440VLJ-40 |
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Similar Description - DP8440VLJ-40 |
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