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DP8464BN-3 Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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DP8464BN-3 Datasheet(HTML) 3 Page - National Semiconductor (TI) |
3 / 26 page DC Electrical Characteristics Over Recommended Operating Temperature and Supply Range VREF e 05V Set Hysteresis e 03V Read Write e 03V unless otherwise noted All pin numbers refer to the 24 pin dual-in-line package (Continued) Symbol Pins Parameter Conditions Min Typ Max Units WRITE MODE ZINAI 67 Amp In Impedance VPIN 11 e20V 50 250 X in Write Mode ICAGCb 16 Pin 16 Current VPIN 11 e20V 1 5 m A in Write Mode VPIN 16 e39V lVPIN 21b VPIN 22 l e13 VDC DIGITAL PINS VIH 1113 High Level Input 2 V Voltage VIL 1113 Low Level Input 08 V Voltage VI 1113 Input Clamp VCC e Min b 15 V Voltage II eb18 mA IIH 1113 High Level Input VCC e Max 20 m A Current VI e 27V II 1113 Input Current at VCC e Max 1 mA Maximum Input VI e 55V Voltage IIL 1113 Low Level Input VCC e Max b 200 m A Current VI e 05V VOH 1214 High Level Output VCC e Min 27 V 15 Voltage IOH eb40 mA (Note 4) VOL 1214 Low Level Output VCC e Min 05 V 15 Voltage IOL e 800 mA (Note 4) IOS 1214 Output Short VCC e Max b 100 mA 15 Circuit Current VO e OV ICC 9 Supply Current VCC e Max 54 75 mA AC Electrical Characteristics Over Recommended Operating Temperature and Supply Range unless otherwise noted Symbol Pins Parameter Conditions Typ Max Units DP8464B-2 14 Pulse Pairing (See Pulse Pairing Set Up) g 15 g 3ns tpp DP8464B-3 14 Pulse Pairing (See Pulse Pairing Set Up) g 2 g 5ns tpp DP8464B-1 14 Pulse Pairing (See Pulse Pairing Set Up) g 05 g 1ns tpp at 25 CVCC e 12V only Note 1 The temperature coefficient of the input impedance is typically 005% per degree C Note 2 The AGC Threshold is defined as the voltage across the Gate Channel Input (pins 21 and 22) when the voltage on CAGC (pin 16) is 42V Note 3 The Set Hysteresis Threshold is defined as the minimum differential AC signal across the Gate Channel Input (pins 21 and 22) which causes the voltage on the Channel Alignment Output (pin 15) to change state Note 4 To prevent inductive coupling from the digital outputs to Amp In the TTL outputs should not drive more than one ALS TTL load each Note 5 The following pins did not meet the 2000V ESD test with the human body model 120 pF thru 15 kX Pins 1 2 3 10 11 12 14 21 24 3 |
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