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DP8441VLJ-40 Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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DP8441VLJ-40 Datasheet(HTML) 7 Page - National Semiconductor (TI) |
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7 / 46 page  30 Signal Descriptions 31 ADDRESS AND CONTROL SIGNALS Pin Device (if not Input Description Name Applicable to All) Output R0 – 11 DP8440 I ROW ADDRESS These inputs are used to specify the row address during an access to the DRAM They are also used to program the chip when ML is asserted R0 – 12 DP8441 C0 – 11 DP8440 I COLUMN ADDRESS These inputs are used to specify the column address during an access to the DRAM They are also used to program the chip when ML is asserted C0 – 12 DP8441 B0–B1 I BANK SELECT Depending on programming these inputs are used to select group RAS and CAS outputs to assert during an access They are also used to program the chip when the ML is asserted ECAS0 – 3 DP8440 I ENABLE CAS These inputs asserted enable a single or group of CAS outputs In combination with the B0 B1 and the programming selection these inputs select which ECAS0 – 7 DP8441 CAS outputs will assert during an access The ECAS signals can also be used to toggle a group of CAS outputs during page or burst mode accesses They are also used to program the chip when ML is asserted NoWRAP I NO WRAP Asserting this signal causes the column address to be incremented sequentially by one The column address will not wrap around if NoWRAP is asserted (EXTNDRF) When RFIP is asserted this signal is an EXTNDRF used to extend refresh by any number of CLK periods until EXTNDRF is negated NoLATCH DP8441 I COLUMN ADDRESS LATCH DISABLE This input will disable ADS from latching the column address when Latch Mode is selected ADS I ADDRESS STROBE This input starts every access Depending on programming this input could latch the column address from the rising edge CS I CHIP SELECT This input signal must be asserted to enable ADS to start an access DTACK O DATA TRANSFER ACKNOWLEDGE This output can be programmed to insert wait states into a CPU access cycle DTACK negated signifies a wait condition when asserted signifies that the access has taken place This signal can be delayed a number of positive or negative edges of clock During burst accesses DTACK transitions increment the column address NADTACK O NEXT ADDRESS or EARLY DTACK This output asserts one clock cycle before DTACK This output can be used to request the next address in a sort of pipelining fashion or it provides more time when DTACK needs to be generated externally WAITIN DP8441 I WAIT INPUT This input asserted delays DTACK for one extra clock period GRANT I MEMORY ACCESS GRANT The GRANT input functions as an output enable If negated it forces the outputs to a TRI-STATE condition PAGMISS IO PAGE MISS When programmed as an output this signal asserts when either the row or the bank address changes from the previous access cycle or the column address has been incremented beyond the page boundary If this pin is programmed as an input it is the responsibility of the system to tell the controller if the next access is within the page Useful for CPUs with internal page comparators PAGMISS is valid only if ADS and CS are asserted BSTARQ I BURST ACCESS REQUEST This input enables the Burst Access Mode This input can be programmed to be active high or active low BSTARQ 7 |
Similar Part No. - DP8441VLJ-40 |
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Similar Description - DP8441VLJ-40 |
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