Electronic Components Datasheet Search |
|
K6X4008T1F-MF85 Datasheet(PDF) 7 Page - Samsung semiconductor |
|
K6X4008T1F-MF85 Datasheet(HTML) 7 Page - Samsung semiconductor |
7 / 9 page K6X4008T1F Family CMOS SRAM Revision 1.0 September 2003 7 TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) Address CS tWC tWR(4) tAS(3) tDW tDH Data Valid WE Data in Data out High-Z High-Z tCW(2) tWP(1) tAW NOTES (WRITE CYCLE) 1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC 2.7V 2.2V VDR CS GND Data Retention Mode CS ≥VCC - 0.2V tSDR tRDR TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) Address CS tCW(2) tWR(4) tWP(1) tDW tDH tOW tWHZ Data Undefined Data Valid WE Data in Data out tWC tAW tAS(3) |
Similar Part No. - K6X4008T1F-MF85 |
|
Similar Description - K6X4008T1F-MF85 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |