clock and uses it to recover the serialized data. ROUT data

is valid when LOCK is low. Otherwise ROUT0–ROUT9 is

invalid.

The ROUT0-ROUT9 pins use the RCLK pin as the reference

to data. The polarity of the RCLK edge is controlled by the

RCLK_R/F input. See

Figure 13.

ROUT(0-9), LOCK and RCLK outputs will drive a maximum

of three CMOS input gates (15 pF load) with a 80 MHz clock.

Resynchronization

When the Deserializer PLL locks to the embedded clock

edge, the Deserializer LOCK pin asserts a low. If the Dese-

rializer loses lock, the LOCK pin output will go high and the

outputs (including RCLK) will enter TRI-STATE.

The user’s system monitors the LOCK pin to detect a loss of

synchronization. Upon detection, the system can arrange to

pulse the Serializer SYNC1 or SYNC2 pin to resynchronize.

Multiple resynchronization approaches are possible. One

recommendation is to provide a feedback loop using the

LOCK pin itself to control the sync request of the Serializer

(SYNC1 or SYNC2). Dual SYNC pins are provided for mul-

tiple control in a multi-drop application. Sending sync pat-

terns for resynchronization is desirable when lock times

within a specific time are critical. However, the Deserializer

can lock to random data, which is discussed in the next

section.

Random Lock Initialization and

Resynchronization

The initialization and resynchronization methods described

in their respective sections are the fastest ways to establish

the link between the Serializer and Deserializer. However,

the SCAN921226 can attain lock to a data stream without

requiring the Serializer to send special SYNC patterns. This

allows the SCAN921226 to operate in “open-loop” applica-

tions. Equally important is the Deserializer’s ability to support

hot insertion into a running backplane. In the open loop or

hot insertion case, we assume the data stream is essentially

random. Therefore, because lock time varies due to data

stream characteristics, we cannot possibly predict exact lock

time. However, please see

Table 1 for some general random

lock times under specific conditions. The primary constraint

on the “random” lock time is the initial phase relation be-

tween the incoming data and the REFCLK when the Dese-

rializer powers up. As described in the next paragraph, the

data contained in the data stream can also affect lock time.

If a specific pattern is repetitive, the Deserializer could enter

“false lock” - falsely recognizing the data pattern as the

clocking bits. We refer to such a pattern as a repetitive

multi-transition, RMT. This occurs when more than one

Low-High transition takes place in a clock cycle over multiple

cycles. This occurs when any bit, except DIN 9, is held at a

low state and the adjacent bit is held high, creating a 0-1

transition. In the worst case, the Deserializer could become

locked to the data pattern rather than the clock. Circuitry

within the SCAN921226 can detect that the possibility of

“false lock” exists. The circuitry accomplishes this by detect-

ing more than one potential position for clocking bits. Upon

detection, the circuitry will prevent the LOCK output from

becoming active until the potential “false lock” pattern

changes. The false lock detect circuitry expects the data will

eventually change, causing the Deserializer to lose lock to

the data pattern and then continue searching for clock bits in

the serial data stream. Graphical representations of RMT are

shown in

Figure 1. Please note that RMT only applies to bits

DIN0-DIN8.

Powerdown

When no data transfer occurs, you can use the Powerdown

state. The Serializer and Deserializer use the Powerdown

state, a low power sleep mode, to reduce power consump-

tion. The Deserializer enters Powerdown when you drive

PWRDN and REN low. The Serializer enters Powerdown

when you drive PWRDN low. In Powerdown, the PLL stops

and the outputs enter TRI-STATE, which disables load cur-

rent and reduces supply current to the milliampere range. To

exit Powerdown, you must drive the PWRDN pin high.

Before valid data exchanges between the Serializer and

Deserializer, you must reinitialize and resynchronize the de-

vices to each other. Initialization of the Serializer takes 510

TCLK cycles. The Deserializer will initialize and assert LOCK

high until lock to the Bus LVDS clock occurs.

TRI-STATE

The Serializer enters TRI-STATE when the DEN pin is driven

low. This puts both driver output pins (DO+ and DO−) into

TRI-STATE. When you drive DEN high, the Serializer returns

to the previous state, as long as all other control pins remain

static (SYNC1, SYNC2, PWRDN, TCLK_R/F).

When you drive the REN pin low, the Deserializer enters

TRI-STATE.

Consequently,

the

receiver

output

pins

(ROUT0–ROUT9) and RCLK will enter TRI-STATE. The

LOCK output remains active, reflecting the state of the PLL.

TABLE 1.

Random Lock Times for the SCAN921226

80 MHz

Units

Maximum

18

µs

Mean

3.0

µs

Minimum

0.43

µs

Conditions:

PRBS 2

1) Difference in lock times are due to different starting points in the data

pattern with multiple parts.

Test Modes

In addition to the IEEE 1149.1 test access to the digital TTL

pins, the SCAN921025 and SCAN921226 have two instruc-

tions to test the LVDS interconnects. The first is EXTEST.

This is implemented at LVDS levels and is only intended as

a go no-go test (e.g. missing cables). The second method is

the RUNBIST instruction. It is an ’at-system-speed’ intercon-

nect test. It is executed in approximately 33mS with a system

clock speed of 66MHz. There are two bits in the RX BIST

data register for notification of PASS/FAIL and TEST_COM-

PLETE. Pass indicates that the BER (Bit-Error-Rate) is bet-

ter than 10

An important detail is that once both devices have the RUN-

BIST instruction loaded into their respective instruction reg-

isters, both devices must move into the RTI state within 4K

system clocks (At a SCLK of 66Mhz and TCK of 1MHz this

allows for 66 TCK cycles). This is not a concern when both

devices are on the same scan chain or LSP, however, it can

be a problem with some multi-drop devices. This test mode

has been simulated and verified using National’s SCAN-

STA111.

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