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DP8459TP-25 Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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DP8459TP-25 Datasheet(HTML) 11 Page - National Semiconductor (TI) |
11 / 35 page FIGURE 8. Capture of Early-Shifted ENCODED READ DATA Pulse FIGURE 9. Capture of Late-Shifted ENCODED READ DATA Pulse DELAY LINE The DP8459 employs an internal silicon delay line to establish synchronization window alignment. The delay is nominally equivalent to one half of the period of the REFERENCE CLOCK waveform, and is variable in fine increments via the Control Register in order to achieve the window strobe function. The Timing Extractor circuitry derives realtive timing information soley from the REFERENCE CLOCK signal and regulates the magnitude of the delay within the Delay Line. TL/F/9322-13 TL/F/9322-14 http:\\www.national.com 11 PrintDate=1996/07/31 PrintTime=11:05:49 ds009322 Rev. No. 1 Proof 11 |
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