SN74ALVC00-Q1

QUADRUPLE 2-INPUT POSITIVE-NAND GATE

SCES490C − SEPTEMBER 2003 − REVISED JANUARY 2008

1

POST OFFICE BOX 655303

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

JESD 17

description/ordering informatiom

The device performs the Boolean function Y = A

• B or Y = A + B in positive logic.

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

40

°Cto85°C

SOIC − D

Tape and reel

SN74ALVC00IDRQ1

ALVC00I

−40

°C to 85°C

TSSOP − PW

Tape and reel

SN74ALVC00IPWRQ1

VA00I

this document, or see the TI web site at www.ti.com.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

OUTPUT

Y

H

H

L

L

XH

X

L

H

logic diagram, each gate (positive logic)

A

B

Y

Copyright

© 2008, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

1Y

2A

2B

2Y

GND

4B

4A

4Y

3B

3A

3Y