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SN74ALVCH162835 Datasheet(PDF) 1 Page - Texas Instruments |
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SN74ALVCH162835 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 16 page www.ti.com FEATURES DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 NC NC Y1 GND Y2 Y3 VCC Y4 Y5 Y6 GND Y7 Y8 Y9 Y10 Y11 Y12 GND Y13 Y14 Y15 VCC Y16 Y17 GND Y18 OE LE GND NC A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 CLK GND DGG, DGV, OR DL PACKAGE (TOP VIEW) NC − No internal connection SN74ALVCH162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES121F – JULY 1997 – REVISED OCTOBER 2004 • Member of the Texas Instruments Widebus™ Family • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process • Output Port Has Equivalent 26- Ω Series Resistors, So No External Resistors Are Required • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) • Latch-Up Performance Exceeds 250 mA Per JESD 17 • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors • Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages NOTE: For tape-and-reel order entry, the DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR. This 18-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. <br/> The output port includes equivalent 26- Ω series resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH162835 is characterized for operation from -40 °C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, EPIC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 1997–2004, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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