TPS70845, TPS70848, TPS70851, TPS70858, TPS70802

DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS

SLVS301B – JUNE 2000 – REVISED OCTOBER 2002

4

POST OFFICE BOX 655303

detailed block diagram – adjustable voltage version

UVLO

Thermal

Shutdown

Shutdown

2.5 V

+

–

Current

Sense

Reference

Vref

Vref

ENA_1

ENA_1

VIN1 (2 Pins)

GND

VIN2 (2 Pins)

VOUT1 (2 Pins)

FB1

(see Note A)

Falling Edge

Delay

VPGD_1

VSENSE1

Rising Edge

Deglitch

Current

Sense

+

–

ENA_2

ENA_2

Vref

PG1

MR

RESET

FB2

(see Note A)

VIN1

Shutdown

VPGD_2

VSENSE2

Rising Edge

Deglitch

PG2

Shutdown

UVLO

VOUT2 (2 Pins)

ENA_1

ENA_2

EN1

EN2

Shutdown

NOTE A: For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the device. For other

implementations, refer to FB terminals connection discussion in the application information section.