PC16550D

www.ti.com

SNLS378C – JUNE 1995 – REVISED MAY 2015

Pin Functions (continued)

PIN

I/O

NAME

PDIP

PLCC

Data Carrier Detect. When low, indicates that the data carrier has been detected by the MODEM

or data set. The DCD signal is a MODEM status input whose condition can be tested by the

CPU reading bit 7 (DCD) of the MODEM Status Register. Bit 7 is the complement of the DCD

signal. Bit 3 (DDCD) of the MODEM Status Register indicates whether the DCD input has

changed state since the previous reading of the MODEM Status Register. DCD has no effect on

the receiver.

DCD

38

42

I

NOTE

Whenever the DCD bit of the MODEM Status Register

changes state, an interrupt is generated if the MODEM

Status Interrupt is enabled.

Driver Disable. This goes low whenever the CPU is reading data from the UART. It can disable

DDIS

23

26

O

or control the direction of a data bus transceiver between the CPU and the UART.

Data Set Ready. When low, this indicates that the MODEM or data set is ready to establish the

communications link with the UART. The DSR signal is a MODEM status input whose condition

can be tested by the CPU reading bit 5 (DSR) of the MODEM Status Register. Bit 5 is the

complement of the DSR signal. Bit 1 (DDSR) of the MODEM Status Register indicates whether

the DSR input has changed state since the previous reading of the MODEM Status Register.

DSR

37

41

I

NOTE

Whenever the DDSR bit of the MODEM Status

Register changes state, an interrupt is generated if the

MODEM Status Interrupt is enabled.

Data Terminal Ready. When low, this informs the MODEM or data set that the UART is ready to

establish a communications link. The DTR output signal can be set to an active low by

DTR

33

37

O

programming bit 0 (DTR) of the MODEM Control Register to a high level. A Master Reset

operation sets this signal to its inactive (high) state. Loop mode operation holds this signal in its

inactive state.

Interrupt. This pin goes high whenever any one of the following interrupt types has an active high

condition and is enabled through the IER Receiver Error Flag; Received Data Available timeout

INTR

30

33

O

(FIFO Mode only); Transmitter Holding Register Empty; and MODEM Status. The INTR signal is

reset low upon the appropriate interrupt service or a Master Reset operation.

Master Reset. When this input is high, it clears all the registers (except the Receiver Buffer,

Transmitter Holding, and Divisor Latches), and the control logic of the UART. The states of

MR

35

39

I

various output signals (SOUT, INTR, OUT 1, OUT 2, RTS, DTR) are affected by an active MR

input (Refer to Table 3) This input is buffered with a TTL-compatible Schmitt Trigger with 0.5-V

typical hysteresis.

Output 1. This user-designated output can be set to an active low by programming bit 2 (OUT 1)

of the MODEM Control Register to a high level. A Master Reset operation sets this signal to its

OUT 1

34

38

O

inactive (high) state. Loop mode operation holds this signal in its inactive state. In the XMOS

parts this will achieve TTL levels.

Output 2. This user-designated output that can be set to an active low by programming bit 3

(OUT 2) of the MODEM Control Register to a high level. A Master Reset operation sets this

OUT 2

31

35

O

signal to its inactive (high) state. Loop mode operation holds this signal in its inactive state. In

the XMOS parts this will achieve TTL levels.

RCLK

9

10

I

Receiver Clock. This input is the 16 x baud rate clock for the receiver section of the chip.

RD

22

25

I

Read. When RD is high or RD is low while the chip is selected, the CPU can read status

information or data from the selected UART register.

NOTE

Only an active RD or RD input is required to transfer

RD

21

24

I

data

from

the

UART

during

a

read

operation.

Therefore, tie either the RD input permanently low or

the RD input permanently high, when it is not used.

Copyright © 1995–2015, Texas Instruments Incorporated

Submit Documentation Feedback

5

Product Folder Links: PC16550D