9th Clock Pulse

SCL

SDA

100 kHz

3.3 V

PCA9515A

5 V

SDA

SCL

400 kHz

SDA1

SCL1

SDA0

SCL0

EN

SDA

SCL

BUS 0

BUS 1

PCA9515A

SCPS150D – DECEMBER 2005 – REVISED JUNE 2014

www.ti.com

9 Application and Implementation

9.1 Typical Application

A typical application is shown in Figure 3. In this example, the system master is running on a 3.3-V bus, while the

slave is connected to a 5-V bus. Both buses run at 100 kHz, unless the slave bus is isolated, and then the

master bus can run at 400 kHz. Master devices can be placed on either bus.

Figure 3. Typical Application

9.1.1 Design Requirements

The PCA9515A is 5.5-V tolerant, so it does not require any additional circuitry to translate between the different

bus voltages.

the falling edge and causes an internal driver on the other side to turn on, thus causing the other side also to go

9.1.2 Detailed Design Procedure

Figure 4 and Figure 5 show the waveforms that are seen in a typical application. If the bus master in Figure 3

writes to the slave through the PCA9515A, Bus 0 has the waveform shown in Figure 4. This looks like a normal

0.5 V, a step in the SDA is seen. After the master has transmitted the ninth clock pulse, the slave releases the

data line.

Figure 4. Bus 0 Waveforms

8

Submit Documentation Feedback

Copyright © 2005–2014, Texas Instruments Incorporated

Product Folder Links: PCA9515A