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PCM1728EG4 Datasheet(PDF) 6 Page - Texas Instruments |
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PCM1728EG4 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 16 page ® 6 PCM1728 SYSTEM CLOCK The system clock for PCM1728 must be either 256fS, 384fS, 512fS or 768fS, where fS is the audio sampling frequency (typically 32kHz, 44.1kHz, 48kHz, or 96kHz). But 768fS at 96kHz is not accepted. The system clock can be either a crystal oscillator placed between XTI (pin 5) and XTO (pin 6), or an external clock input to XTI. If an external system clock is used, XTO is open (floating). Figure 1 illustrates the typical system clock connections. PCM1728 has a system clock detection circuit which auto- matically senses if the system clock is operating at 256fS ~ 768fS. The system clock should be synchronized with LRCIN (pin 1) clock. LRCIN (left-right clock) operates at the sam- pling frequency fS. In the event these clocks are not synchro- nized, PCM1728 can compensate for the phase difference internally. If the phase difference between left-right and system clocks is greater than 6-bit clocks (BCKIN), the synchronization is performed internally. While the synchro- nization is processing, the analog output is forced to a DC level at bipolar zero. The synchronization typically occurs in less than 1 cycle of LRCIN. SYSTEM CLOCK FREQUENCY - MHz SAMPLING RATE FREQUENCY (fS) - LRCIN 256fS 384fS 512fS 768fS 32kHz 8.1920 12.2880 16.3840 24.5760 44.1kHz 11.2896 16.9340 22.5792 33.8688(1) 48kHz 12.2880 18.4320 24.5760 36.8640(1) 96kHz 24.5760 36.8640(1) 49.1520(1) — NOTE: (1) The internal crystal oscillator frequency cannot be larger than 24.576MHz. TABLE I. Typical System Clock Frequency. Typical input system clock frequencies to the PCM1728 are shown in Table I, also, external input clock timing require- ments are shown in Figure 2. FIGURE 1. System Clock Connection. FIGURE 2. XTI Clock Timing. System Clock (256/384/ 512/768f S) Externl Clock Input CLKO XTI XTO 4 5 6 PCM1728 System Clock Buffer Out Crystal Resonator Oscillation CLKO XTI XTO 4 5 6 PCM1728 XTAL C 1 C 2 C 1 C2 : 10pF ~ 30pF Buffer t SCKH System Clock Pulse Width High t SCKIH : 7ns MIN System Clock Pulse Width Low t SCKIL : 7ns MIN t SCKL 2.0V 0.8V “H” “L” XTI DATA INTERFACE FORMATS Digital audio data is interfaced to PCM1728 on pins 1, 2, and 3, LRCIN (left-right clock), DIN (data input) and BCKIN (bit clock). PCM1728 can accept both standard, I2S, and left justified data formats. Figure 3 illustrates acceptable input data formats. Figure 4 shows required timing specification for digital audio data. Reset PCM1728 has both internal power-on reset circuit and the RST pin (pin 22), which accepts an external forced reset by RST = LOW. For internal power on reset, initialization is done automatically at power on VDD >2.2V (typ). During internal reset = LOW, the output of the DAC is invalid and the analog outputs are forced to VCC /2. Figure 5 illustrates the timing of the internal power on reset. PCM1728 accepts an external forced reset when RST = LOW. When RST = LOW, the output of the DAC is invalid and the analog outputs are forced to VCC/2 after internal initialization (1024 system clocks count after RST = HIGH.) Figure 6 illustrates the timing of the RST pin. Zero Out (pin 21) If the input data is continuously zero for 65536 cycles of BCK, an internal FET is switched to “ON”. The drain of the internal FET is the zero-pin, it will enable “wired-or” with external circuit. |
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