®

PCM1750

8

occurs during the SAMPLE period (see the timing diagram

shown in Figure 2). These errors are stored on the AC

coupling capacitors (CAZ1 to CAZ4, shown in Figure 1)

between the gain stages. During the SAMPLE period the

inputs to gain stages A1 and A2 and the latch are grounded

by switches H1, H2, and AZ1 to AZ4. Capacitors CAZ1 and

CAZ2 track the amplified offset voltage of gain stage A1

and capacitors CAZ3 and CAZ4 do the same for A2. At the

beginning of a conversion cycle, the autozeroing switches

open and the instantaneous amplified value of both the DC

offset voltage and the low-frequency flicker noise is stored

on the coupling capacitors to produce zero comparator offset

during a conversion cycle.

SUCCESSIVE APPROXIMATION

CONVERSION PROCESS

The timing diagram in Figure 2 illustrates the successive

approximation routine of the PCM1750. Control signals

CONVERT and CLK are derived from a master system

frequency of 48kHz) clock used by the optional digital filter.

There are 64 clocks shown in the timing diagram because the

PCM1750 is shown operating at 4 times the standard 48kHz

sample rate (192kHz).

Several events occur on the rising edge of the CONVERT

command. Switches AZ1 to AZ4, H1 and H2 open and

analog common (see Figure 1). This terminates the com-

parator auto-zero cycle and simultaneously switches (co-

phase sampling) both converters from tracking their respec-

tive input signals into the HOLD mode, thus capturing the

the aperture time).

At the start of a conversion cycle when S1 is switched to

divider action of Cl = C2 + C3 + ... C18. In a somewhat

The 19-bit shift register, shown in Figure 4, controls testing

of the bits of the dual ADCs beginning with bit-1 (MSB) and

proceeding one bit at a time to bit-18 (LSB), leaving ON

those bits that don’t cause the cumulative value of the

CDAC to exceed the original input value and leaving OFF

those bits that do. Since the bits of both channels are tested

together, only one shift register is required to control both

ranks of 18 data latches.

For example, the testing of bit-2 proceeds in the following

manner. The positive pulse from the second shift register

element SR2, (see Figure 2 and 4) is applied to the bit-2 data

latch and NOR gate. The NOR gate in turn drives S2 and

switches bit-2 at the beginning of the bit-2 test interval. Note

that the bit interval must be long enough to allow both the

comparator input to settle and the comparator to respond. On

1

2

18

19

3

*Optional

Digital Filter

54 55 56

57 58 59 60

61 62 63 64

1

23

4

5

6

78

9

10 11 12

T1

T4

T6

T3

T5

T7

T9

REF

T

Convert

Ext Clk In

SOUT

Bit 18

LSB

Bit 1

MSB

Bit 2

Bit 17

T8

T2

PARAMETER

DESCRIPTION

MIN

NOMINAL

MAX

UNITS

T1

(1 x TREF)

Convert Command High

24

33

55

% of T4

T2

(6 x TREF)

S/H Acquisition Time

420

486

ns

T3

(4 x TREF)

Convert to Clock time

281

326

1302

ns

T4

(3 x TREF)

Master Clock Input

211

244

977

ns

T5

(1 x TREF)

Clock High

24

33

55

% of T4

T6

(2 x TREF)

Clock Low

45

67

76

% of T4

T7

Data Hold Time

10

ns

T8

Data Setup Time

100

ns

T9

Data Valid Time

120

154

1212

ns

TCONV (64 x TREF)

Conversion Throughput Time

4.5

5.2

20.8

µs

TREF (Sample Rate /64)

Ext Digital Filter Clock

70

81

326

ns

Note: The nominal timing shown in this diagram is all done automatically by the DF1750 digital filter. Only the

optional digital filter clock is required when the DF1750 is used.

FIGURE 3. PCM1750 Setup and Hold Timing Diagram.