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OZ965G Datasheet(PDF) 2 Page - List of Unclassifed Manufacturers |
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OZ965G Datasheet(HTML) 2 Page - List of Unclassifed Manufacturers |
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2 / 7 page  OZ965 OZ965-SF-3.0 Page 2 FUNCTIONAL BLOCK DIAGRAM Refer to the functional block diagram in Figure 2, below, and the Pin Description Table on page 3. Power is transferred to the transformer primary by the N-MOSFET, driven by the MOSFET gate driver out of pin NDR. The P-MOSFET resets the primary field, driven by pin PDR. The usual design results in approximately 50% duty cycle at full lamp intensity. Terminating the NDR signal earlier than the full brightness lamp pulse width performs lamp dimming, using the analog dimming. The voltages on pins HCLMP and LCLMP set a threshold voltage for the ramp comparator setting the maximum duty cycle for NDR. A pulse generator circuit creates the clock signal with the frequency determined by an external, constant current setting resistor (RT) and timing capacitor (CT). The “soft-start” circuit ensures a reliable and long lamp life starting condition. “Soft start” gradually increases the energy delivered to the secondary. When the OZ965 is enabled at pin ENA, the capacitor on pin SST determines the duration of the “soft-start” period, gradually increasing the NDR pulse width to the regulated brightness. The “soft-start” period provides sufficient time for the lamp to ignite. For system reliability there are several circuit protections provided. To ensure a controlled output, the secondary current is monitored on pin FB and is compared to a reference voltage on pin ADJ. The NDR signal is shortened or lengthened dependent upon this feedback. Protection is provided by the resultant signal, CMP, monitoring for a lamp removal condition. Short circuit protection is provided at pin SCP. The OPS signal selects either HCLMP or LCLMP providing current protection against an “Open Lamp” condition at start-up. The OPS signal also allows adjustment to different transformer models. To reduce power dissipation, the switch (MOSFET) drive signals are “break-before-make” with a short, fixed off time between activation of NDR or PDR. Note: OVP – Over Voltage Protection SCP – Short-Circuit Protection UVL – Under Voltage Lockout Figure 2. Functional Block Diagram SCP NDRV ZVS CONTROLLER PDRV SST NDR PDR Vdd ENA OPS CT RT REF IBIAS & REFERENCE 2.50V HCLMP LCLMP ADJ FB CMP GND PULSE GEN ACTIVE "HIGH" - EA + - + LAMP ON/OFF Vmax Vmin (fix value) V V>Vmax -- -> Vmax Vmin<V<Vmax ->V V<Vmin -- ->Vmin UNDER VOLTAGE LOCKOUT t1+t2 (slow start) PROTECTION + - COMP COMP COMP COMP t1 (slow start) RAMP COMP. Vmax=2.6V-Vset COMP Vset 3 4 2 5 6 7 1 10 16 15 14 13 12 11 9 8 POFF POFF 2.5V 0.5V 0.6V SS2 UVLO OLPROT ENABLE Pgate 2.5V Ngate RESET SS1 Vdd 1.5V SS1 V_SS2 MN1 R2 4K I=2.5uA I=12uA R4 70k R5 630k - + - + - + - + - + R1 300k |
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