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SPT9689BIP Datasheet(PDF) 4 Page - Fairchild Semiconductor |
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SPT9689BIP Datasheet(HTML) 4 Page - Fairchild Semiconductor |
4 / 8 page 4 2/20/01 SPT9689 SWITCHING TERMS (Refer to figure 1) tpdH INPUT TO OUTPUT HIGH DELAY – the propaga- tion delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output LOW to HIGH transition tpdL INPUT TO OUTPUT LOW DELAY – the propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output HIGH to LOW transition tpLOH LATCH ENABLE TO OUTPUT HIGH DELAY – the propagation delay measured from the 50% point of the Latch Enable signal LOW to HIGH transition to the 50% point of an output LOW to HIGH transition VOD VOLTAGE OVERDRIVE – the difference between the differential input and reference input voltages tpLOL LATCH ENABLE TO OUTPUT LOW DELAY – the propagation delay measured from the 50% point of the Latch Enable signal LOW to HIGH transition to the 50% point of an output HIGH to LOW transition tH MINIMUM HOLD TIME – the minimum time after the negative transition of the Latch Enable signal that the input signal must remain unchanged in order to be acquired and held at the outputs tpL MINIMUM LATCH ENABLE PULSE WIDTH – the minimum time that the Latch Enable signal must be HIGH in order to acquire an input signal change tS MINIMUM SET-UP TIME – the minimum time before the negative transition of the Latch Enable signal that an input signal change must be present in order to be acquired and held at the outputs GENERAL INFORMATION The SPT9689 is an ultrahigh-speed dual voltage com- parator. It offers tight absolute characteristics. The device has differential analog inputs and complementary logic outputs compatible with ECL systems. The output stage is adequate for driving terminated 50 ohm transmission lines. The SPT9689 has a complementary latch enable control for each comparator. Both should be driven by standard ECL logic levels. The negative common mode voltage is –2.5 V. The posi- tive common mode voltage is +4.0 V. The dual comparators share the same VCC and VEE con- nections but have separate grounds for each comparator to achieve high crosstalk rejection. ECL OUT Q Q REF 1 REF 2 PRE AMP + VIN CLK BUF LATCH VIN VEE GND LE LE VCC Figure 2 – Internal Function Diagram |
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