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TPS40057PWP Datasheet(PDF) 11 Page - Texas Instruments |
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TPS40057PWP Datasheet(HTML) 11 Page - Texas Instruments |
11 / 33 page TPS40054 TPS40055 TPS40057 SLUS593B − DECEMBER 2003 − REVISED APRIL 2004 11 www.ti.com APPLICATION INFORMATION Once the soft-start is initiated, the UVLO cicruit must see a total count of seven cycles in which the ramp duration is longer than the clock cycle before an undervoltage condition is declared. (See Figure 4). UDG−02132 Clock PWM RAMP PowerGood VIN UVLO Threshold 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 Figure 4. Undervoltage Lockout Operation The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the device at 10% below the nominal start up voltage, the maximum duty cycle is reduced approximately 10% at the nominal start up voltage. The impedance of the input voltage can cause the input voltage, at the controller, to sag when the converter starts to operate and draw current from the input source. Therefore, there is voltage hysteresis that prevents nuisance shutdowns at the UVLO point. With RT chosen to select the operating frequency and RKFF chosen to select the start−up voltage, the approximate amount of hysteresis voltage is shown in Figure 5. 10 0.2 0 15 20 25 30 35 40 0.6 0.4 0.8 1.2 1.0 VUVLO − Undevoltage Lockout Threshold − V UNDERVOLTAGE LOCKOUT THRESHOLD vs HYSTERESIS Figure 5. |
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