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SN74LVC540ADWG4 Datasheet(PDF) 9 Page - Texas Instruments |
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SN74LVC540ADWG4 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 26 page OE1 OE2 To Seven Other Channels A1 Y1 1 19 2 18 SN54LVC540A, SN74LVC540A www.ti.com SCAS297N – JANUARY 1993 – REVISED JUNE 2014 9 Detailed Description 9.1 Overview These devices are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package that facilitate printed circuit board layout. The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2) input is high, all outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 9.2 Functional Block Diagram Figure 4. Logic Diagram (Positive Logic) 9.3 Feature Description • Wide operating voltage range – Operates from 1.65 V to 3.6 V • Allows down voltage translation – Inputs accept voltages to 5.5 V • Ioff Feature – Allows voltages on the inputs and outputs when VCC is 0 V 9.4 Device Functional Modes Table 1. Function Table INPUTS OUTPUT Y OE1 OE2 A L L L H L L H L H X X Z X H X Z Copyright © 1993–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: SN54LVC540A SN74LVC540A |
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