D

Q

Q

CLR

PRE

CLK

GND

VCC

3 V

MCU

A

Y

NC

GND

VCC

3 V

SN74LVC1G74

SN74LVC1G17

3 V

SN74LVC1G74

SCES794E – OCTOBER 2009 – REVISED JANUARY 2015

www.ti.com

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the

other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time

requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,

data at the D input can be changed without affecting the levels at the outputs.

The resistor and capacitor at the CLR pin are optional. If they are not used, the CLR pin should be connected

10.2 Typical Power Button Circuit

Figure 4. Device Power Button Circuit

10.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus

contention because it can drive currents that would exceed maximum limits. Outputs can be combined to

produce higher drive but the high drive will also create faster edges into light loads so routing and load conditions

should be considered to prevent ringing.

10.2.2 Detailed Design Procedure

1. Recommended Input Conditions:

–

For rise time and fall time specifications, see (

Δt/ΔV) in Recommended Operating Conditions table.

–

–

2. Recommend Output Conditions:

–

Load currents should not exceed 50 mA per output and 100 mA total for the part.

–

Series resistors on the output may be used if the user desires to slow the output edge signal or limit the

10

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