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SN74LVC1G74RSER Datasheet(PDF) 9 Page - Texas Instruments |
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SN74LVC1G74RSER Datasheet(HTML) 9 Page - Texas Instruments |
9 / 24 page TG C C TG C C TG C C C TG C C PRE CLK D CLR Q Q C 7 2 6 5 3 1 SN74LVC1G74 www.ti.com SCES794E – OCTOBER 2009 – REVISED JANUARY 2015 9 Detailed Description 9.1 Overview This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 9.2 Functional Block Diagram 9.3 Feature Description • Allow down voltage translation – 5 V to 3.3 V – 5.0 V to 1.8 V – 3.3 V to 1.8 V • Inputs accept voltage levels up to 5.5 V • Ioff Feature – Can prevent backflow current that can damage device when powered down 9.4 Device Functional Modes Table 1. Function Table INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H(1) H(1) H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 (1) This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: SN74LVC1G74 |
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