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HY29LV160BF-70I Datasheet(PDF) 9 Page - Hynix Semiconductor |
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HY29LV160BF-70I Datasheet(HTML) 9 Page - Hynix Semiconductor |
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9 / 48 page  9 Rev. 1.2/May 01 HY29LV160 Write Operation Certain operations, including programming data and erasing sectors of memory, require the host to write a command or command sequence to the HY29LV160. Writes to the device are performed by placing the byte or word address on the device’s address inputs while the data to be written is input on DQ[15:0] (BYTE# = High) or DQ[7:0] (BYTE# = Low). The host system must drive the CE# and WE# pins Low and drive OE# High for a valid write operation to take place. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. The “Device Commands” section of this data sheet provides details on the specific device commands implemented in the HY29LV160. Standby Operation When the system is not reading or writing to the device, it can place the HY29LV160 in the Standby mode. In this mode, current consumption is greatly reduced, and the data bus outputs are placed in the high impedance state, independent of the OE# input. The Standby mode can be invoked using two methods. The device enters the CE# Deep Standby mode when the CE# and RESET# pins are both held at V CC ± 0.3V. Note that this is a more restricted voltage range than V IH . If both CE# and RESET# are held at V IH, but not within VCC ± 0.3V, the de- vice will be in the CE# Normal Standby mode, but the standby current will be greater. The device enters the RESET# Deep Standby mode when the RESET# pin is held at V SS ± 0.3V. If RESET# is held at V IL but not within VSS ± 0.3V, the device will be in the RESET# Normal Standby mode, but the standby current will be greater. See Reset Operation for additional information. The device requires standard access time (t CE) for read access when the device is in either of the standby modes, before it is ready to read data. If the device is deselected during erasure or pro- gramming, it continues to draw active current until the operation is completed. Sleep Mode The sleep mode automatically minimizes device power consumption. This mode is automatically entered when addresses remain stable for t ACC + 30 ns (typical) and is independent of the state of the CE#, WE#, and OE# control signals. Stan- dard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. NOTE: Sleep mode is entered only when the device is in read mode. It is not entered if the device is executing an automatic algorithm, if it is in erase suspend mode, or during receipt of a command sequence. Output Disable Operation When the OE# input is at V IH, output data from the device is disabled and the data bus pins are placed in the high impedance state. Reset Operation The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for the minimum specified period, the device immediately termi- nates any operation in progress, tri-states the data bus pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. If an operation was interrupted by the as- sertion of RESET#, it should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. Current is reduced for the duration of the RESET# pulse as described in the Standby Operation sec- tion above. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains Low (busy) until the internal reset operation is complete, which re- quires a time of t READY (during Automatic Algo- rithms). The system can thus monitor RY/BY# to determine when the reset operation completes, and can perform a read or write operation t RB after RY/BY# goes High. If RESET# is asserted when a program or erase operation is not executing (RY/ BY# pin is High), the reset operation is completed within a time of t RP. In this case, the host can per- form a read or write operation t RH after the RE- SET# pin returns High . The RESET# pin may be tied to the system reset signal. Thus, a system reset would also reset the device, enabling the system to read the boot-up firmware from the Flash memory. |
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