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SN74LVC2G74MDCUTEP Datasheet(PDF) 1 Page - Texas Instruments |
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SN74LVC2G74MDCUTEP Datasheet(HTML) 1 Page - Texas Instruments |
1 / 12 page 1 FEATURES DCUPACKAGE (TOP VIEW) 3 6 CLR Q 8 1 V CC CLK 5 GND 4 Q 2 7 PRE D DESCRIPTION/ORDERING INFORMATION SN74LVC2G74-EP www.ti.com ....................................................................................................................................................................................................... SCES718 – MAY 2008 SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET • Controlled Baseline • Inputs Accept Voltages to 5.5 V – One Assembly Site • Max t pd of 7.9 ns at 3.3 V – One Test Site • Low Power Consumption, 10 µA Max I CC – One Fabrication Site • ±24 mA Output Drive at 3.3 V • Extended Temperature Performance of –55°C • Typical V OLP (Output Ground Bounce) to 125 °C <0.8 V at VCC = 3.3 V, TA = 25°C • Enhanced Diminishing Manufacturing Sources • Typical V OHV (Output VOH Undershoot) (DMS) Support >2 V at VCC = 3.3 V, TA = 25°C • Enhanced Product-Change Notification • I off Supports Partial Power Down Mode Operation • Qualification Pedigree (1) • Latch-Up Performance Exceeds 100 mA Per • Supports 5-V V CC Operation JESD 78, Class II (1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an • ESD Protection Exceeds JESD 22 extended temperature range. This includes, but is not limited – 2000-V Human-Body Model (A114-A) to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, – 200-V Machine Model (A115-A) electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as – 1000-V Charged-Device Model (C101) justifying use of this component beyond specified performance and environmental limits. This single positive edge triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial power down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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