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SN74LVC2G86 Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LVC2G86 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 17 page = 2k 2k + 1 LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT ODD-PARITY ELEMENT The output is active (low) if all inputs stand at the same logic level (i.e., A = B). The output is active (low) if an even number of inputs (i.e., 0 or 2) are active. The output is active (high) if an odd number of inputs (i.e., only 1 of the 2) are active. = 1 EXCLUSIVE OR These are five equivalent exclusive-OR symbols valid for an SN74LVC2G86 gate in positive logic; negation may be shown at any two ports. SN74LVC2G86 SCES360I – AUGUST 2001 – REVISED DECEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Function Table (Each Gate) INPUTS OUTPUT Y A B L L L L H H H L H H H L EXCLUSIVE-OR LOGIC An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. 2 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G86 |
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