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LMC555CM Datasheet(PDF) 3 Page - Texas Instruments |
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LMC555CM Datasheet(HTML) 3 Page - Texas Instruments |
3 / 28 page 3 LMC555 www.ti.com SNAS558M – FEBRUARY 2000 – REVISED JULY 2016 Product Folder Links: LMC555 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated 5 Pin Configuration and Functions D, DGK, and P Packages 8-Pin SOIC, VSSOP, and PDIP (Top View) YPB Package 8-Pin DSBGA (Top View) Pin Functions PIN I/O DESCRIPTION SOIC, VSSOP, and PDIP NO. DSBGA NO. NAME 1 A3 GND O Ground reference voltage 2 B3 Trigger I Responsible for transition of the flip-flop from set to reset. The output of the timer depends on the amplitude of the external trigger pulse applied to this pin 3 C3 Output O Output driven waveform 4 C2 Reset I Negative pulse applied to this pin to disable or reset the timer. When not used for reset purposes, it should be connected to VCC to avoid false triggering 5 C1 Control Voltage I Control voltage controls the threshold and trigger levels. It determines the pulse width of the output waveform. An external voltage applied to this pin can also be used to modulate the output waveform 6 B1 Threshold I Compares the voltage applied to the terminal with a reference voltage of 2/3 Vcc. The amplitude of voltage applied to this terminal is responsible for the set state of the flip-flop. 7 A1 Discharge I Open collector output which discharges a capacitor between intervals (in phase with output). It toggles the output from high to low when voltage reaches 2/3 of the supply voltage 8 A2 V+ I Supply voltage with respect to GND |
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