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LM8327 Datasheet(PDF) 7 Page - Texas Instruments |
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LM8327 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 65 page  LM8327 www.ti.com SNLS329A – SEPTEMBER 2011 – REVISED MAY 2013 Table 1. Definition of Terms used in Serial Command Example Term Bits Description S START Condition (always generated from the master device) ADDRESS 7 Slave address of LM8327 sent from the host This bit determines if the following data transfer is from master to slave (data write) or from slave to master (data read). R/W 1 0: Write 1: Read An acknowledge bit is mandatory and must be appended on each byte transfer. The Acknowledge status ACK 1 is actually provided from the slave and indicates to the master that the byte transfer was successful. The first byte after sending the slave address is the REGISTER byte which contains the physical address REG 8 the host wants to read from or write to. RS Repeated START condition DATA 8 The DATA field contains information to be stored into a register or information read from a register. Not Acknowledge Bit. The Not Acknowledge status is assigned from the Master receiving data from a NACK 1 slave. The NACK status will actually be assigned from the master in order to signal the end of a communication cycle transfer P STOP condition (always generated from the master device). All actions associated with the non-shaded boxes in Figure 4 are controlled from the master (host) device. All actions associated with the shaded boxes in Figure 4 are controlled from the slave (LM8327) device. The master device can send subsequent REGISTER addresses separated by Repeated START conditions. A STOP condition must be set from the master at the very end of a communication cycle. It is recommended to use Repeated START conditions in multi-Master systems when sending subsequent REGISTER addresses. This technique will make sure that the master device communicating with the LM8327 will not loose bus arbitration. Starting a Communication Cycle There are two reasons for the host device to start communication to the LM8327: 1. The LM8327 device has set the IRQN line low in order to signal a key - event or any other condition which initializes a hardware interrupt from LM8327 to the host. 2. The host device wants to set a GENIO port, read from a GENIO port, configure a GENIO port, and read the status from a register or initialize any other function which is supported from the LM8327. In case a GENIO shall be read it will be most likely, that the LM8327 device will be residing in “sleep mode”. In this mode the system clock will be off to establish the lowest possible current consumption. If the host device starts the communication under this condition the LM8327 device will not be able to acknowledge the first attempt of sending the slave address. The LM8327 will wake up because of the START condition but it can’t establish the internal timing to scan the first byte received. The master device must therefore apply a second attempt to start the communication with the LM8327 device. Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM8327 |
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