LM8328_16 datasheet(6/56 Pages) TI1

Part #	LM8328

Description	LM8328 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface

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LM8328

SNLS328A – AUGUST 2011 – REVISED MARCH 2013

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HALT MODE

HALT MODE DESCRIPTION

The fully static architecture of the LM8328 allows stopping the internal RC clock in Halt mode, which reduces

power consumption to the minimum level. Figure 3 shows the current in Halt mode at the maximum VCC (1.98V)

from 25°C to +85°C.

Figure 3. Halt Current vs. Temperature at 1.98V

Halt mode is entered when no key-press event, key-release event, or ACCESS.bus activity is detected for a

certain period of time (by default, 1020 milliseconds). The mechanism for entering Halt mode is always enabled

in hardware, but the host can program the period of inactivity which triggers entry into Halt mode using the

autosleep function. (See Table 47.)

ACCESS.BUS ACTIVITY

When the LM8328 is in Halt mode, only activity on the ACCESS.bus interface that matches its Slave Address will

cause the LM8328 to exit from Halt mode. However, the LM8328 will not be able to acknowledge the first bus

cycle immediately following wake-up from Halt mode. It will respond with a negative acknowledgement, and the

host should then repeat the cycle. A peripheral that is continuously active can share the bus since this activity will

not prevent the LM8328 from entering Halt mode.

LM8328 PROGRAMMING INTERFACE

The LM8328 operation is controlled from a host device by a complete register set, accessed via the I2C-

compatible ACCESS.bus interface. The ACCESS.bus communication is based on a READ/WRITE structure,

following the I2C transmission protocol. All functions can be controlled by configuring one or multiple registers.

Please refer to LM8328 REGISTER SET for the complete register set.

ACCESS.BUS COMMUNICATION

Figure 4 shows a typical read cycle initiated by the host.)

Figure 4. Master/Slave Serial Communication (Host to LM8328)

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