SN75C185

LOW-POWER MULTIPLE DRIVERS AND RECEIVERS

SLLS065F – AUGUST 1989 – REVISED JANUARY 2000

5

POST OFFICE BOX 655303

DRIVER SECTION

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VOH

High level output voltage

VIL = 0.8 V,

RL = 3 kΩ, VDD = 5 V,

VSS = – 5 V

4

4.5

V

VOH

High-level output voltage

IL

,

See Figure 1

L

,

VDD = 12 V

VSS = – 12 V

10

10.8

V

VOL

Low-level output voltage

VIH = 0.8 V,

RL = 3 kΩ, VDD = 5 V,

VSS = – 5 V

– 4.4

–4

V

VOL

g

(see Note 3)

IH

,

See Figure 1

L

,

VDD = 12 V

VSS = – 12 V

– 10.7

–10

V

IIH

High-level input current

VI = 5 V,

See Figure 2

1

µA

IIL

Low-level input current

VI = 0,

See Figure 2

–1

µA

IOS(H)

High-level short-circuit

VI = 0.8 V,

VO = 0 or VO = VSS,

45

12

19 5

mA

IOS(H)

g

output current (see Note 4)

I

,

See FIgure 1

O

O

SS,

– 4.5

– 12

– 19.5

mA

IOS(L)

Low-level short-circuit

VI = 2 V,

VO = 0 or VO = VDD,

45

12

19 5

mA

IOS(L)

output current (see Note 4)

I

,

See Figure 1

OO

DD,

4.5

12

19.5

mA

ro

Output resistance

VDD = VSS = VCC = 0,

See Note 5

VO = – 2 V to 2 V,

300

400

Ω

† All typical values are at TA = 25°C.

NOTES:

3. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic

levels only, e.g., if – 10 V is a maximum, the typical value is a more negative voltage.

4. Not more than one output should be shorted at one time.

5. Test conditions are those specified by TIA/EIA-232-F.

noted) (see Figure 3)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPLH

Propagation delay time,

low- to high-level output (see Note 6)

1.2

3

µs

tPHL

Propagation delay time,

high- to low-level output (see Note 6)

RL = 3 kΩ to 7 kΩ,

CL = 15 pF

2.5

3.5

µs

tTLH

Transition time, low- to high-level output

0.53

2

3.2

µs

tTHL

Transition time, high- to low-level output

0.53

2

3.2

µs

tTLH

Transition time, low- to high-level output (see Note 7)

RL =3kΩ to7kΩ

CL = 2500 pF

1

µs

tTHL

Transition time, high- to low-level output (see Note 7)

RL = 3 kΩ to 7 kΩ,

CL = 2500 pF

1

µs

SR

Output slew rate (see Note 7)

RL = 3 kΩ to 7 kΩ,

CL = 15 pF

4

10

30

V/

µs

NOTES: 6.

tPHL and tPLH include the additional time due to on-chip slew rate and are measured at the 50% points.

7.

Measured between 3-V and – 3-V points of output waveform TIA/EIA-232-F conditions), and all unused inputs are tied either high

or low.