SN54LVTH16835, SN74LVTH16835

3.3-V ABT 18-BIT UNIVERSAL BUS DRIVERS

WITH 3-STATE OUTPUTS

SCBS713C – MARCH 1998 – REVISED APRIL 1999

6

POST OFFICE BOX 655303

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figure 1)

SN54LVTH16835

SN74LVTH16835

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

150

150

150

150

MHz

t

Pulse duration

LE high

3.3

3.3

3.3

3.3

ns

tw

Pulse duration

CLK high or low

3.3

3.3

3.3

3.3

ns

Data before CLK

↑

2.2

2.5

2.1

2.4

tsu

Setup time

Data before LE

↓

CLK high

2.5

1.7

2.3

1.5

ns

Data before LE

↓

CLK low

1.5

0.5

1.5

0.5

th

Hold time

Data after CLK

↑

1

0

1

0

ns

th

Hold time

Data after LE

↓

0.8

0.8

0.8

0.8

ns

(unless otherwise noted) (see Figure 1)

SN54LVTH16835

SN74LVTH16835

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

MIN

MAX

MIN

MAX

MIN

TYP†

MAX

MIN

MAX

fmax

150

150

150

150

MHz

tPLH

A

Y

1.2

3.9

4.3

1.3

2.6

3.7

4

ns

tPHL

A

Y

1.2

3.9

4.3

1.3

2.4

3.7

4

ns

tPLH

LE

Y

1.4

5.3

5.9

1.5

3.2

5.1

5.7

ns

tPHL

LE

Y

1.4

5.3

5.9

1.5

3.3

5.1

5.7

ns

tPLH

CLK

Y

1.4

5.3

5.9

1.5

3.5

5.1

5.7

ns

tPHL

CLK

Y

1.4

5.3

5.9

1.5

3.4

5.1

5.7

ns

tPZH

OE

Y

1.2

5

5.9

1.3

2.9

4.6

5.5

ns

tPZL

OE

Y

1.2

5

5.9

1.3

3

4.6

5.5

ns

tPHZ

OE

Y

1.6

6

6.5

1.7

4.2

5.8

6.3

ns

tPLZ

OE

Y

1.6

6

6.5

1.7

3.7

5.8

6.3

ns

† All typical values are at VCC = 3.3 V, TA = 25°C.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.