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P4C1024SSPT Datasheet(PDF) 6 Page - Pyramid Semiconductor Corporation |
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P4C1024SSPT Datasheet(HTML) 6 Page - Pyramid Semiconductor Corporation |
6 / 8 page P4C1024 Page 6 of 14 Document # SRAM124 REV A AC CHARACTERISTICS—WRITE CYCLE (V CC = 5V ± 10%, All Temperature Ranges) (2) Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max tWC Write Cycle Time 15 20 25 35 45 55 70 85 100 120 ns tCW Chip Enable Time to End of Write 12 15 18 22 30 35 45 50 60 75 ns tAW Address Valid to End of Write 12 15 20 25 35 45 60 70 85 100 ns tAS Address Set-up Time 000 00 00 00 0 ns tWP Write Pulse Width 12 15 18 22 25 30 40 45 55 70 ns tAH Address Hold Time 000 00 00 00 0 ns tDW Data Valid to End of Write 7 8 10 15 20 25 30 35 45 60 ns tDH Date Hold Time 000 00 00 00 0 ns tWZ Write Enable to Output in High Z 8 101115 1820 2530 4050 ns tOW Output Active from End of Write 333 33 33 33 3 ns Symbol Parameter -15 -20 -25 -35 -45 Unit -55 -70 -85 -100 -120 Notes: 11. CE 1 and WE must be LOW, and CE2 HIGH for WRITE cycle. 12. OE is LOW for this WRITE cycle to show t WZ and tOW. 13. If CE 1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH, the output remains in a high impedance state. 14. Write Cycle Time is measured from the last valid address to the first transitioning address. TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE WE WE WE WE CONTROLLED)(11) |
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