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LMF100CIWM Datasheet(PDF) 9 Page - Texas Instruments |
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LMF100CIWM Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 42 page  Not Recommended for New Designs LMF100 www.ti.com SNOSBG9B – JULY 1999 – REVISED JUNE 2015 Logic Input Characteristics (continued) All limits apply to TA = TJ = 25°C unless otherwise specified. LMF100CCN LMF100CIWM PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX 1.5 Tested Limit (1) MIN Logical “1” TMIN to TMAX 1.5 V V + = +2.5 V, V− = −2.5 V, Design Limit (2) TMIN to TMAX 1.5 −1.5 Tested Limit (1) MAX Logical “0” VLSh = 0 V TMIN to TMAX −1.5 V Design Limit (2) TMIN to TMAX −1.5 CMOS Clock Input Voltage 4 Tested Limit (1) MIN Logical “1” TMIN to TMAX 4 V V + = +5 V, V− = 0 V, Design Limit (2) TMIN to TMAX 4 1 Tested Limit (1) MAX Logical “0” VLSh = +2.5 V TMIN to TMAX 1 V Design Limit (2) TMIN to TMAX 1 2 Tested Limit (1) MIN Logical “1” TMIN to TMAX 2 V V + = +5 V, V− = 0 V, Design Limit (2) TMIN to TMAX 2 TTL Clock Input Voltage 0.8 Tested Limit (1) MAX Logical “0” TMIN to TMAX 0.8 V VLSh = 0 V, VD + = 0 V Design Limit (2) TMIN to TMAX 0.8 Copyright © 1999–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LMF100 |
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