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LMH0395 Datasheet(PDF) 5 Page - Texas Instruments

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Part # LMH0395
Description  3G HD/SD SDI Dual Output Low Power Extended Reach Adaptive Cable Equalizer
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

LMH0395 Datasheet(HTML) 5 Page - Texas Instruments

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LMH0395
www.ti.com
SNLS323M – AUGUST 2010 – REVISED JULY 2015
Pin Functions – SPI Mode / SPI_EN = VCC
(1) (continued)
PIN
I/O, TYPE
DESCRIPTION
NO.
NAME
SPI register access enable
This pin has an internal pulldown.
6
SPI_EN
I, LVCMOS
H = SPI register access mode
L = Pin mode
Output driver 1 (SDO1, SDO1) disable
This pin has an internal pullup
7
SDO1_DISABLE
I, LVCMOS
H (or no connection) = Output driver 1 is in a high-impedance state.
L = Output driver 1 is enabled.
8
AEC+
I/O, Analog
AEC loop filter external capacitor (1-µF) positive connection (capacitor is optional)
9
AEC-
I/O, Analog
AEC loop filter external capacitor (1-µF) negative connection (capacitor is optional)
Carrier detect
10
CD
O, LVCMOS
H = No input signal detected.
L = Input signal detected.
Mute reference input that sets the threshold for CD and (with CD tied to MUTE) and
11
MUTEREF
I, Analog
determines the maximum cable to be equalized before muting. MUTEREF may be either
unconnected or connected to ground for normal CD operation.
12
VEE
Ground
Negative power supply (ground)
SPI slave select
13
SS (SPI)
I, LVCMOS
This pin has an internal pullup.
14
SDO0
O, LVDS
Serial data output 0 complement
15
SDO0
O, LVDS
Serial data output 0 true
16
VEE
Ground
Negative power supply (ground)
17
SDO1
O, LVDS
Serial data output 1 complement
18
SDO1
O, LVDS
Serial data output 1 true
SPI Master Input / Slave Output
19
MISO (SPI)
O, LVCMOS
LMH0395 control data transmit
20
VCC
Power
Positive power supply (+2.5 V)
21
SCK (SPI)
I, LVCMOS
SPI serial clock input
SPI Master Output / Slave Input
22
MOSI (SPI)
I, LVCMOS
LMH0395 control data receive
This pin has an internal pulldown.
23
VEE
Ground
Negative power supply (ground)
24
VCC
Power
Positive power supply (+2.5 V)
Connect exposed DAP to negative power supply (ground). See Figure 22 for layout
DAP
VEE
Ground
example.
Copyright © 2010–2015, Texas Instruments Incorporated
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