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SN75DP159RSBT Datasheet(PDF) 7 Page - Texas Instruments |
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SN75DP159RSBT Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 63 page  7 SN65DP159, SN75DP159 www.ti.com SLLSEJ2C – JULY 2015 – REVISED JULY 2016 Product Folder Links: SN65DP159 SN75DP159 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Pin Functions (continued) PIN I/O DESCRIPTION (1) SIGNAL NAME RGZ RSB SWAP/POL (2) 1 N/A I 3 level (1) Input lane SWAP and polarity control pin when I2C_EN/PIN = Low SWAP/POL = H receive lane polarity swap (retimer mode only) SWAP/POL = L receive lanes swap (retimer and redriver mode) SWAP/POL = No Connect normal working SUPPLY AND GROUND PINS VCC 13, 43 11, 37 P 3.3-V power supply VDD 14, 23, 24, 37, 48 12, 19, 20, 31, 40 P 1.1-V power supply GND 7, 19, 41, 30, Thermal Pad 15, 35, Thermal Pad G Ground (1) (H) Logic high (pin strapped to VCC through 65-k Ω resistor); (L) logic low (pin strapped to GND through 65-kΩ resistor); (for mid-level, no connect) (2) Blue pin names are only in the SNx5DP159 RGZ package. (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential voltages, are with respect to network ground terminal. (3) Tested in accordance with JEDEC Standard 22, Test Method A114-B. 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted) (1) (2) MIN MAX UNIT Supply voltage(3) VCC –0.3 4 V VDD –0.3 1.4 V Voltage Main link input (IN_Dx AC-coupled mode), AUX_SRCp, AUX_SRCn differential voltage 1.56 V TMDS outputs ( OUT_Dx) –0.3 4 V HPD_SRC, Vsadj, SDA_CTL, SCL_CTL, OE, HDMI_SEL/A1, EQ_SEL/A0, I2C_EN/PIN, SLEW_CTL, TX_TERM_CTL, SDA_SRC, SCL_SRC –0.3 4 V HPD_SNK, SDA_SNK, SCL_SNK –0.3 6 V Continuous power dissipation See Thermal Information Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 V |
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