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PI4MSD5V9543A Datasheet(PDF) 9 Page - Pericom Semiconductor Corporation |
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PI4MSD5V9543A Datasheet(HTML) 9 Page - Pericom Semiconductor Corporation |
9 / 13 page ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2015-07-0034 PT0524-4 8/18/15 9 PI4MSD5V9543A 2 Channel I2C bus switch with Interrupt Logic and Reset Voltage translation The pass gate transistors of the PI4MSD5V9543A are constructed such that the VCC voltage can be used to limit the maximum voltage that is passed from one I2C-bus to another. Figure 6:Vpass voltage VS Vcc Figure 6 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data specified in Section “DC Electrical characteristics” of this data sheet). In order for the PI4MSD5V9543A to act as a voltage translator, the Vpass voltage should be equal to, or lower than the lowest bus voltage. For example, if the main bus was running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vpass should be equal to or below 2.7 V to clamp the downstream bus voltages effectively. Looking at Figure 6, we see that Vpass (max) is at 2.7 V when the PI4MSD5V9543A supply voltage is 3.5 V or lower so the PI4MSD5V9543A supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels I2C BUS The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time are interpreted as control signals Figure 7: Bit Transfer |
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