SRC4184IPAGR datasheet(6/43 Pages) TI1

Part #	SRC4184IPAGR

Description	4-Channel, Asynchronous Sample Rate Converter

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Manufacturer	TI1 [Texas Instruments]

Direct Link	http://www.ti.com

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SRC4184

SBFS026B − JUNE 2004 − REVISED SEPTEMBER 2007

www.ti.com

6

PIN DESCRIPTIONS

PIN #

NAME

I/O

DESCRIPTION

1

IFMTA0

Input

SRC A Audio Input Data Format(1)

2

IFMTA1

Input

SRC A Audio Input Data Format(1)

3

IFMTA2

Input

SRC A Audio Input Data Format(1)

4

OFMTA0

Input

SRC A Audio Output Data Format(1)

5

OFMTA1

Input

SRC A Audio Output Data Format(1)

6

OWLA0

Input

SRC A Audio Output Data Word Length(1)

7

OWLA1

Input

SRC A Audio Output Data Word Length(1)

8

BYPA

Input

SRC A Bypass Mode (Active High)

9

LGRPA0

Input

SRC A Low Group Delay Mode(1)

10

LGRPA1

Input

SRC A Low Group Delay Mode(1)

11

DDNA

Input

SRC A Direct Downsampling Mode (Active High)(1)

12

DEMA0

Input

SRC A Digital De-Emphasis Filter Mode(1)

13

DEMA1

Input

SRC A Digital De-Emphasis Filter Mode(1)

14

MODEA0

Input

SRC A Serial Port Mode(1)

15

MODEA1

Input

SRC A Serial Port Mode(1)

16

MODEA2

Input

SRC A Serial Port Mode(1)

17

RATIOA

Output

SRC A Ratio Flag

18

RDYA

Output

SRC A Ready Flag (Active Low)

19

MUTEA

Input

SRC A Output Soft Mute

20

RCKIA

Input

SRC A Reference Clock

21

RST

Input

Reset and Power-Down (Active Low)

22

H/S

Input

Control Mode (0 = Software, 1 = Hardware)

23

DGND

Ground

Digital Ground

24, 25

VDD33

Power

Core Supply, +3.3V. Required when REGEN is high. When REGEN is low, VDD33 must be left unconnected.

26

REGEN

Input

Voltage Regulator Enable (Active High)

27, 28

VDD18

Power

Core Supply, +1.8V. Required when REGEN is low. When REGEN is high, VDD18 must be left unconnected.

29

RCKIB

Input

SRC B Reference Clock

30

MUTEB

Input

SRC B Output Soft Mute

31

RDYB

Output

SRC B Ready Flag (Active Low)

32

RATIOB

Output

SRC B Ratio Flag

33

MODEB2 or CDIN

Input

SRC B Serial Port Mode(1) or SPI Port Serial Data Input(2)

34

MODEB1 or CCLK

Input

SRC B Serial Port Mode(1) or SPI Port Data Clock(2)

35

MODEB0 or CS

Input

SRC B Serial Port Mode(1) or SPI Port Chip Select (Active Low)(2)

36

DEMB1 or CDOUT

I/O

SRC B Digital De-Emphasis Filter Mode(1) or SPI Port Serial Data Output(2)

37

DEMB0

Input

SRC B Digital De-Emphasis Filter Mode(1)

38

DDNB

Input

SRC B Direct Downsampling Mode (Active High)(1)

39

LGRPB1

Input

SRC B Low Group Delay Mode(1)

40

LGRPB0

Input

SRC B Low Group Delay Mode(1)

41

BYPB

Input

SRC B Bypass Mode (Active High)

42

OWLB1

Input

SRC B Audio Output Data Word Length(1)

43

OWLB0

Input

SRC B Audio Output Data Word Length(1)

44

OFMTB1

Input

SRC B Audio Output Data Format(1)

45

OFMTB0

Input

SRC B Audio Output Data Format(1)

46

IFMTB2

Input

SRC B Audio Input Data Format(1)

47

IFMTB1

Input

SRC B Audio Input Data Format(1)

48

IFMTB0

Input

SRC B Audio Input Data Format(1)

49

SDOUTB

Output

SRC B Audio Output Data

50

BCKOB

I/O

SRC B Audio Output Bit Clock

51

LRCKOB

I/O

SRC B Audio Output Left/Right or Word Clock

52

TDMIB

Input

SRC B TDM Input Data (TDM Format Only)

53

BCKIB

I/O

SRC B Audio Input Bit Clock

54

LRCKIB

I/O

SRC B Audio Input Left/Right or Word Clock

55

SDINB

Input

SRC B Audio Input Data

56

VIO

Power

Digital I/O Supply, +1.65V to +3.6V

57

DGND

Ground

Digital Ground

58

SDINA

Input

SRC A Audio Input Data

59

LRCKIA

I/O

SRC A Audio Input Left/Right or Word Clock

60

BCKIA

I/O

SRC A Audio Input Bit Clock

61

TDMIA

Input

SRC A TDM Input Data (TDM Format Only)

62

LRCKOA

I/O

SRC A Audio Output Left/Right or Word Clock

63

BCKOA

I/O

SRC A Audio Output Bit Clock

64

SDOUTA

Output

SRC A Audio Output Data

(1) Disabled in Software control mode.

(2) Disabled in Hardware control mode.

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