1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

D+

D

-

V

BUS

DGNDU

HID0

HID1

HID2

SEL0

SEL1

V

CCCI

AGNDC

V L

IN

V R

IN

V

COM

SSPND

DIN

V

CCXI

AGNDX

XTO

V

CCP2I

DGND

V

CCP1I

V

L

OUT

XTI

DOUT

V

DDI

AGNDP

V

R

OUT

PCM2902C

PCM2900C

PCM2902C

www.ti.com

SBFS039

– SEPTEMBER 2011

PCM2902C PIN ASSIGNMENTS

DB PACKAGE

SSOP-28

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Table 2. PCM2902C TERMINAL FUNCTIONS

TERMINAL

NAME

NO.

I/O

DESCRIPTION

AGNDC

11

–

Analog ground for codec

AGNDP

18

–

Analog ground for PLL

AGNDX

22

–

Analog ground for oscillator

D

–

2

I/O

USB differential input/output minus

(1)

D+

1

I/O

USB differential input/output plus

(1)

DGND

26

–

Digital ground

DGNDU

4

–

Digital ground for USB transceiver

DIN

24

I

S/PDIF input

(2)

DOUT

25

O

S/PDIF output

HID0

5

I

HID key state input (mute), active high

(3)

HID1

6

I

HID key state input (volume up), active high

(3)

HID2

7

I

HID key state input (volume down), active high

(3)

SEL0

8

I

Must be set to high

(4)

SEL1

9

I

Must be set to high

(4)

SSPND

28

O

Suspend flag, active-low (low: suspend, high: operational)

3

–

10

–

Internal analog power supply for codec

(5)

17

–

Internal analog power supply for PLL

(5)

19

–

Internal analog power supply for PLL

(5)

23

–

Internal analog power supply for oscillator

(5)

14

–

(5)

27

–

Internal digital power supply

12

I

ADC analog input for L-channel

13

I

ADC analog input for R-channel

16

O

DAC analog output for L-channel

15

O

DAC analog output for R-channel

XTI

21

I

Crystal oscillator input

(6)

XTO

20

O

Crystal oscillator output

(1)

LV-TTL level.

(2)

3.3-V CMOS-level input with internal pull-down, 5-V tolerant.

(3)

3.3-V CMOS-level input with internal pull-down. This pin informs the PC of serviceable control signals such as mute, volume up, or

volume down, which have no connection with the internal DAC or ADC directly. See the Interface #3 and End-Points sections.

(4)

TTL Schmitt trigger, 5-V tolerant.

(5)

Connect a decoupling capacitor to GND.

(6)

3.3-V, CMOS-level input.

Copyright

© 2011, Texas Instruments Incorporated

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