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PGA204BU Datasheet(PDF) 11 Page - Texas Instruments |
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PGA204BU Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 20 page  11 ® PGA204/205 A 1 A 2 A 3 12 11 10 25k Ω 25k Ω 25k Ω 25k Ω 7 PGA204 PGA205 Resistors can be substituted for REF200. Power supply rejection will be degraded. Feedback Digitally Selected Feedback Network 6 V O2 V+ V O = G (VIN – VIN) + VREF +– OPA177 V+ 10k Ω 100 Ω 100 Ω V– V REF ±10mV Adjustment Range Output Offset Adjustment 5 14 16 4 V IN V IN – + 15 A 1 A 0 Digital Ground 200k Ω to 1M Ω Input Offset Adjustment Trim Range ≈ ±250µV 13 V+ 1 V O1 9 8 V– Over-Voltage Protection Over-Voltage Protection 100µA 1/2 REF200 100µA 1/2 REF200 1.3mA flows in the digital ground pin. It is good practice to return digital ground through a separate connection path so that analog ground is not affected by the digital ground current. The digital inputs, A0 and A1, are not latched; a change in logic inputs immediately selects a new gain. Switching time of the logic is approximately 1 µs. The time to respond to gain change is effectively the time it takes the amplifier to settle to a new output voltage in the newly selected gain (see settling time specifications). Many applications use an external logic latch to access gain control data from a high speed data bus (see Figure 7). Using an external latch isolates the high speed digital bus from sensitive analog circuitry. Locate the latch circuitry as far as practical from analog circuitry. Some applications select gain of the PGA204/205 with switches or jumpers. Figure 2 shows pull-up resistors con- nected to assure a noise-free logic “1” when the switch, jumper or open-collector logic is open or off. Fixed-gain applications can connect the logic inputs directly to V+ or V– (or other valid logic level); no resistor is required. OFFSET VOLTAGE Voltage offset of the PGA204/205 consists of two compo- nents—input stage offset and output stage offset. Both components are specified in the specification table in equa- tion form: VOS = VOSI + VOSO / G (1) where: VOS total is the combined offset, referred to the input. VOSI is the offset voltage of the input stage, A1 and A2. VOSO is the offset voltage of the output difference amplifier, A3. VOSI and VOSO do not change with gain. The composite offset voltage VOS changes with gain because of the gain term in equation 1. Input stage offset dominates in high gain (G ≥100); both sources of offset may contribute at low gain (G=1 to 10). OFFSET TRIMMING Both the input and output stages are laser trimmed for very low offset voltage and drift. Many applications require no external offset adjustment. Figure 3 shows an optional input offset voltage trim circuit. This circuit should be used to adjust only the input stage offset voltage of the PGA204/205. Do this by programming FIGURE 2. Switch or Jumper-Selected Digital Inputs. A 1 A 2 7 5 14 16 4 V IN V IN – + Over-Voltage Protection Over-Voltage Protection Digitally Selected Feedback Network 15 6 9 V O2 V OS Adj Digital ground can alternatively be connected to V– power supply. V+ 100k Ω 100k Ω Switches, jumpers or open-collector logic output. FIGURE 3. Optional Offset Voltage Trim Circuit. |
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