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LMK01801 Datasheet(PDF) 4 Page - Texas Instruments |
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LMK01801 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 51 page LMK01801 SNAS573A – JANUARY 2012 – REVISED APRIL 2013 www.ti.com 2 Device Information 2.1 Functional Configurations Table 2-1. Clock Output Configurations Output Outputs in Bank Input Clock Group CLKoutX/CLK Output Type Divider Ratios Delay Divider Group outX* CG1 0 to 3 LVDS/LVPECL 0 to 3 1 to 8 No CLKin0/CLKin0 A LVDS/LVPECL/ * CG2 4 to 7 4 to 7 1 to 8 No LVCMOS LVDS/LVPECL/ CG3 8 to 11 8 to 11 1 to 8 No LVCMOS CLKin1/CLKin1 B Digital and * LVDS/LVPECL/ 1 to 1045 CG4 12 and 13 12 and 13 Analog LVCMOS (1) (2) (1) Digital Delay will not work if CLKout12_13_DIV = 1. (2) See Section 3.4 Table 2-2. Pin Control Mode for EN_PIN_CTRL = Low Pin Output Groups Pin=Low Pin=Middle Pin=High CLKoutTYPE_0 CLKout0 to CLKout3 LVDS Powerdown LVPECL CLKoutTYPE_1 CLKout4 to CLKout7 LVDS LVCOMS (Norm/Inv) LVPECL CLKoutTYPE_2 CLKout8 to CLKout13 LVDS LVCMOS (Norm/Inv) LVPECL CLKout0 to CLKoutDIV_0 ÷ 1 ÷ 4 ÷ 2 CLKout3 Divider CLKout4 to CLKoutDIV_1 ÷ 1 ÷ 4 ÷ 2 CLKout7 Divider CLKout8 to ÷ 1 ÷ 4 ÷ 2 CLKout11 Divider CLKoutDIV_2 CLKout12 to ÷ 8 ÷ 512 ÷ 16 CLKout13 Divider Table 2-3. Pin Control Mode for EN_PIN_CTRL = High(1)(2) Pin Output Groups Pin=Low Pin=Middle Pin=High CLKout0 to CLKout3 LVPECL CLKoutTYPE_0 LVDS LVPECL CLKout4 to CLkout7 LVCMOS (Norm/Inv) CLKoutTYPE_1 CLKout8 to CLKout11 LVDS LVCMOS (Norm/Inv) LVPECL CLKoutTYPE_2 CLKout12 to CLKout13 LVDS LVCMOS (Norm/Inv) LVPECL CLKout0 to CLKoutDIV_0 ÷ 1 ÷ 4 ÷ 2 CLKout7 Dividers CLKout8 to CLKoutDIV_1 ÷ 1 ÷ 4 ÷ 2 CLKout11 Divider CLKout12 to CLKoutDIV_2 ÷ 4 ÷ 512 ÷ 16 CLKout13 Divider (1) Digital Delay will not work if CLKout12_13_DIV = 1. (2) See Section 3.4 4 Device Information Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK01801 |
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