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TAS3108IA Datasheet(PDF) 7 Page - Texas Instruments |
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TAS3108IA Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 63 page  www.ti.com 3.2 Terminal Descriptions 3.3 Reset (RESET) TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 TERMINAL PULLUP/ INPUT/ DESCRIPTION PULLDOWN(2) OUTPUT(1) NAME NO. AVDD 38 I Analog power supply (3.3 V) AVSS 1 Analog ground CS0 7 I Pulldown Chip select DVDD 9, 30 I Digital power supply input (3.3 V) DVSS 10, 29 Digital ground GPIO 8 I/O Pullup GPIO control (user programmable) LRCLK 19 I/O Pulldown Sample rate clock (fS) MCLKIN 5 I Master clock input (connect to ground when not in use) MCLKO 21 O Master clock output MICROCLK_DIV 6 I Pulldown Internal microprocessor clock divide control Power down. Powers down all logic and stops all clocks, active low. PDN 31 I Pullup Coefficient memory remains stable through the power-down cycle. PLL0 34 I Pullup PLL control 0 PLL1 35 I Pulldown PLL control 1 PLL2 36 I Pullup PLL control 2 RESERVED 33, 37 Reserved. Connect to ground RESET 32 I Pullup Reset, active low SCL1 16 I/O I2C port 1 clock (always a slave) SCL2 18 I/O I2C port 2 clock (always a master) SCLKIN 20 I Pulldown Bit clock input SCLKOUT1 22 O Bit clock 1 out. Used to receive input serial data. SCLKOUT2 23 O Bit clock 2 out. Used to clock output serial data. SDA1 15 I/O I2C port 1 data (always a slave) SDA2 17 I/O I2C port 2 data (always a master) SDIN1 11 I Pulldown Serial data input 1 SDIN2 12 I Pulldown Serial data input 2 SDIN3 13 I Pulldown Serial data input 3 SDIN4 14 I Pulldown Serial data input 4 SDOUT1 27 O Serial data output 1 SDOUT2 26 O Serial data output 2 SDOUT3 25 O Serial data output 3 SDOUT4 24 O Serial data output 4 VR_PLL 2 Internal regulator. This pin must not be used to power external devices. XTALI 3 O Oscillator input (connect to ground when not in use) XTALO 4 O Oscillator output VR_DIG 28 Internal regulator. This pin must not be used to power external devices. (1) I = input, O = output (2) All pullups are 20- µA weak pullups, and all pulldowns are 20-µA weak pulldowns. The pullups and pulldowns are included to ensure proper input logic levels if the terminals are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input). Devices that drive inputs with pullups must be able to sink 20 µA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be able to source 20 µA while maintaining a logic-1 drive level. The RESET pin is an asynchronous control signal that restores all TAS3108/TAS3108IA components to the default configuration. When a reset occurs, the audio DSP core is put into an idle state and the 8051 starts initialization. A valid MCLKI or XTLI must be present when clearing the RESET pin to initiate a device reset. A reset can be initiated by applying a logic 0 on RESET. A reset can also be issued at power turnon by the three internal power supplies. Submit Documentation Feedback Physical Characteristics 7 Not Recommended for New Designs |
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